Globespan Virata Corporation

Globespan, Inc.

Wenwei Pan

Yue-Peng Zheng

Jian Wang

Lujing Cai

Daniel Amrany

Marc R Delvaux

William J Santulli

A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses. In its broadest terms, the method can be described as: identifying a block data length, N, and an interleaver/de-interleaver depth, D; initializing a set of pointers associated with each of N memory segments; initializing a set of pointer maximum values responsive to the relative magnitude of N and D, identifying a memory index responsive to a base address and the set of pointer maximum values; using a memory segment identifier, a word identifier, and a byte identifier along with the memory index and the pointers to write/read the bytes of code words.

System and method for efficient convolutional interleaving/de-interleaving

A circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation is disclosed. The single modulo pointer of the present invention may be used to increase data throughput through a data interleaver/deinterleaver. A memory address pointer consistent with the present invention may be implemented with a multiplexer, an adder, a counter, and a modulo operator. A method for convolutional interleaving/deinterleaving is also disclosed.

Circuit and method for convolutional interleaving using a single modulo operation

A resource optimized interleaving/deinterleaving system comprising a Reed-Solomon encoder, a Reed-Solomon decoder, a state machine, and a memory is disclosed. Reed-Solomon encoded fastpath data is stored in memory. A stream of interleaved data with predefined parameters S, the number of DMT symbols per each Reed-Solomon codeword, D, the interleaving depth, and N, the block length is written into system memory at an adaptable rate determined by the Reed-Solomon encoder. The previously stored Reed-Solomon encoded fastpath data is automatically reassembled and buffered with the interleaved data to form appropriate DMT transmission symbols. The DMT transmission symbols are then read out of the system memory at a rate determined by the next processing function, i.e., tone ordering. A method of using one Reed-Solomon encoder/decoder with the integrated interleaving/deinterleaving system to support dual single latency DMT systems is also disclosed.

System and method for resource optimized integrated forward error correction in a DMT communication system

Disclosed is an RS decoder controller and method, the system comprising a codeword length register to indicate a number of symbols in a number of RS codewords to be decoded by the RS decoder, a error correction capability configuration register to indicate a number of error symbols that are corrected by the RS decoder, and a modulation scheme associated register to indicate a modulation scheme associated employed to generate the RS codewords. The RS decoder controller further includes a number of state machines to control the operation of a Galois field computation unit in the RS decoder.

Configurable Reed-Solomon controller and method

Disclosed is a configurable Galois field computation system and method, the system comprising a read bus and a write bus with a memory coupled therebetween. In addition, a logical circuit is coupled between the read and write busses, the logical circuit having a number of data calculation configurations that are established to generate an n symbol codeword from a number of symbols in a syndrome array. The logical circuit is placed in the various data calculation configurations in order to perform the various operations involved with Reed-Solomon decoding.

Galois field computation system and method

Disclosed is a configurable Reed-Solomon (RS) decoder that comprises a parallel multiply accumulator having a data input to receive at least one RS codeword, the parallel multiply accumulator being configured to generate a syndrome array from the RS codeword. The configurable RS decoder also includes a Galois field computation unit coupled to the parallel multiply accumulator, and an RS decoder controller coupled to the parallel multiply accumulator and the Galois field computation unit, wherein the RS decoder controller controls the operation of the parallel multiply accumulator and the Galois field computation unit. The RS decoder may be configured for different numbers of symbols in the RS codewords, parity symbols in the RS codewords, and modulation types employed in creating the RS codewords.

Configurable decoder and method for decoding a reed-solomon codeword

Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

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Ocean Township, NJ, United States of America

Wenwei Pan