Pericom Semiconductor Corporation

Wensong Chen

Paul C F Tong

Ping Ping Xu

Zhi Qing Liu

Siu-Weng Simon Wong

Zhiqing Liu

A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Active ESD shunt with transistor feedback to reduce latch-up susceptibility

A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching

ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

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San Jose, CA, United States of America

Wensong Chen