Zhuhai Access Semiconductor Co., Ltd

Nexperia B.v.

Wenshi Wang

Lei Feng

Benxia Huang

Xianming Chen

Jindong Feng

Lina Jiang

Minxiong Li

Jiangjiang Zhao

Bingsen Xie

Yuan Li

Min Gu

Weiyuan Yang

Shigui Xin

Frank Burmeister

Yujun Zhao

Jinxin Yi

Edward Tena

A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.

Package substrate manufacturing method

An inductor-integrating embedded support frame according to an embodiment of the present disclosure includes a core dielectric layer, a through-opening penetrating through the core dielectric layer, wherein the through-opening is used for embedding and installing a device, and an inductor, wherein the inductor includes a magnetic core embedded in the core dielectric layer and an inductance coil wound around the magnetic core, wherein at least one conductive copper pillar penetrating through the core dielectric layer is provided at the periphery of the through-opening and the inductor.

Inductor-integrating embedded support frame and substrate, and manufacturing method thereof

Disclosed are a method for manufacturing a support frame structure and a support frame structure. The support frame structure is used for embedded packaging, and includes: a metal plate comprising a support region and an opening region, at least one upper dielectric hole and at least one lower dielectric hole being formed respectively in upper and lower surfaces of the support region, the upper dielectric hole being communicated with the lower dielectric hole; at least one set of metal pillars comprising an upper metal pillar and a lower metal pillar, the upper metal pillar and the lower metal pillar being vertically connected to upper and lower surfaces of the metal plate, respectively; a dielectric layer comprising an upper dielectric layer and a lower dielectric layer, the upper dielectric layer and the lower dielectric layer being correspondingly formed on the upper surface of the metal plate and the upper dielectric hole and on a lower surface of the metal plate and the lower dielectric hole, respectively; and at least one core embedding cavity arranged in the opening region, running through the dielectric layer and the metal plate, and spaced from the upper dielectric hole and the lower dielectric hole by the dielectric layer.

Support frame structure and manufacturing method thereof

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Embedded chip package and manufacturing method thereof

A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Circuit prearranged heat dissipation embedded packaging structure and manufacturing method thereof

A packaging structure with an antenna and a manufacturing method thereof are disclosed. The packaging structure includes a package, an antenna circuit, an interconnecting circuit, an outer-layer circuit, and a chip. The package is internally packaged with a first conducting through hole column and a second conducting through hole column. The antenna circuit is disposed on a first surface and a sidewall of the package. The interconnecting circuit is packaged in the package, and is connected to the antenna circuit by the first conducting through hole column. The outer-layer circuit is disposed on a second surface of the package, and is connected to the interconnecting circuit by the second conducting through hole column. The outer-layer circuit is further connected to a conductive pin. The chip is packaged in the package, and is connected to the interconnecting circuit or the outer-layer circuit.

Packaging structure with antenna and manufacturing method thereof

Disclosed is a manufacturing method for an embedded structure. The method includes: preparing a temporary carrier board; preparing a second circuit layer on at least one of the upper surface and the lower surface of the temporary carrier board, and preparing a first dielectric layer to cover the second circuit layer; patterning and curing the first dielectric layer to form a cavity, mounting a device in the cavity, and performing hot-curing, wherein a surface of the device provided with a terminal faces an opening of the cavity; and preparing a second dielectric layer, wherein the device is embedded in the second dielectric layer, and a surface of the second dielectric layer is higher than a surface of the terminal by a preset value.

Embedded structure, manufacturing method thereof and substrate

An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.

A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.

Cavity substrate having directional optoelectronic transmission channel and manufacturing method thereof

Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity.

Embedded packaging structure having shielding cavity and manufacturing method thereof

An embedded packaging method capable of realizing heat dissipation, includes: providing a frame having at least one through hole; attaching a tape on the first surface and placing a device in the through hole; completely filling the through hole with photosensitive insulating material, and completely curing the photosensitive insulating material in a lower portion of the through hole while not completely curing the photosensitive insulating material in an upper portion of the through hole and covered on the second surface; electroplating on the first surface to form a first metal layer, and electroplating on the upper surface and a side surface of the device, an upper surface of the photosensitive insulating material and an upper end face of each of the first copper pillars to form a second metal layer; and etching to obtain a first circuit layer and a second circuit layer, respectively.

Growing community of inventors

Zhuhai, China

Wenshi Wang