Macronix International Co., Ltd.

Wenpin Lu

Mam-Tsung Wang

Ming-Shang Chen

Ying-Che Lo

Uway Tseng

Shaw Hung Ku

Chun-Lien Su

Ming Shang Chen

Baw-Chyuan Lin

Chia Wei Wu

Ming-Hung Chou

Hung-Yu Chiu

Chia-Shing Chen

Tzung Ting Han

Shih Chin Lee

Ten Hao Yeh

Shang Wei Lin

Ching-Yu Chang

Tao-Cheng Lu

Yin Jen Chen

Tahui Wang

Shao Hong Ku

Ming-Jye Chiou

A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell; a drain region in the substrate, a portion of the drain region being under the second side of the multi-bit charge-trapping cell; and a channel region in the substrate between the source region and the drain region. The channel region has one of a p-type doping and an n-type doping, and the doping is configured to provide a highest doping concentration near the central portion of the channel region.

Nonvolatile memory device and method of forming the same

A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

Design tool for charge trapping memory using simulated programming operations

A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Flash memory having insulating liners between source/drain lines and channels

A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.

Non-volatile memory device having a nitride barrier to reduce the fast erase effect

Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold voltage from drifting significantly higher. A soft hot electron program is used to selected nitride storage memory cells that have been detected to have a threshold voltage that is higher than a presetting threshold voltage (EV) minus a wordline delta X. The effect of the soft electron program neutralizes the excess holes introduced by erasure of nitride storage memory cells that decreases the amount of threshold voltage from drifting higher. In one embodiment, a hole annealing method describes a soft hot electron programming to nitride storage memory cells in a block of nitride memory array that have been determined to have a threshold voltage higher than the presetting threshold voltage minus the wordline delta X.

Hole annealing methods of non-volatile memory cells

A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

Method of fabricating a memory device having a self-aligned contact

A method of reducing charge loss for nonvolatile memory. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate, and a thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining on the semiconductor substrate from prior manufacturing processes. Finally, a metal layer is formed on the dielectric layer.

Method of reducing charge loss for nonvolatile memory

Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM

Method for soft-programming at least one floating gate memory cell in at least one page of a persistent memory device by converging the low threshold voltages of the several cells of the page within an optimal range, and apparatus implementing the method. The methodology of the present invention teaches connecting the individual drains of the several memory cells of the device of a given page, or block, to a voltage limited constant current circuitry component. The methodology applies a first positive voltage to the word line of the page and a second positive voltage to the common source in a fixed time period to converge the pages low threshold voltage distribution. The methodology is capable of implementation on either the source or drain side of the memory array.

Auto-stopped page soft-programming method with voltage limited component

An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited. The load may be a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.

Apparatus and method for programming of flash EPROM memory

A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.

Virtual ground flash cell with asymmetrically placed source and drain

A device and method of operation for an improved erase-verify device in which the non-selected cells, within a bit line column of an array of cells, remain inactive. Only the active cell is verified with minimum bit line column leakage associated with the operation of erase verification. Erase verification for a memory array is achieved by applying a source voltage (generally positive) to the common source line associated with a column of cells in the array. This will raise the threshold voltages of the cells (through the body effect of the semiconductor device) to a level higher than the predetermined minimum erased threshold voltage. The non-selected wordlines are coupled to a reference level below the threshold level of the cell (e.g. ground), and the selected wordline is coupled to a positive voltage which is a function of the source voltage. The source voltage is also added to the drain source voltage. The source voltage thereby serves as a feedback input to both the wordline and bit line inputs. Thereafter, a fixed drain-to-source bias is applied to the selected bit line column to conduct current for verification of the cell. The source voltage feedback allows the wordline voltage to be adjusted so that read current through the selected cell can be maintained at a desired level. Using this approach, the bit line column leakage caused by over-erased cells can be effectively suppressed, and an accurate verification result can be achieved.

Device and method for suppressing bit line column leakage during erase

A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.

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Hsinchu, Taiwan

Wenpin Lu