Actel Corporation, Inc.

Other

Wenn-Jei Chen

Steve S Chiang

Abdul R Forouhi

Yeouchung Yen

Frank W Hawley

Linda Liu

Huan-Chung Tseng

Esam Elashmawi

Yeochung Yen

Yeouchung Yan

Huang-Chung Tseng

A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500.degree. C.-950.degree. C.) and may be carried out in the range of 400.degree. C.-950.degree. C. making it compatible with a wide range of processes.

Dielectric-polysilicon-dielectric-polysilicon-dielectric antifuse for

A process electrostatic discharge ('ESD') protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step. It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage. When processing is complete, the protection cell is biased off and has no effect on the remaining antifuses. According to a second aspect of the present invention, a deep valley topography is created under a bottom electrode of the protection cell. Because the cell is deeper than the other antifuse cells while retaining the same cell opening size, the step coverage within the protection cell will be reduced and the protection cell will have a lower breakdown voltage than the regular antifuse cells formed with it. In all other respects, it operates as set forth regarding the first aspect of the invention.

Process ESD protection devices for use with antifuses

An antifuse fabrication process includes the steps of forming a lower antifuse electrode, forming an insulating layer over the lower antifuse electrode, forming an antifuse aperture in the insulating layer, forming a dielectric antifuse material including a first layer comprising silicon dioxide and a second layer comprising silicon nitride over the antifuse insulating layer, etching the silicon nitride layer to form a small layer of silicon nitride in a region centered over the antifuse aperture, optionally forming a third dielectric antifuse layer comprising silicon dioxide, and forming an upper antifuse electrode. Alternatively, the first, second, and third layers of dielectric antifuse material may be formed and then etched to form a small composite sandwich structure of silicon nitride and silicon dioxide over the first silicon dioxide layer in a region centered over the antifuse aperture prior to forming an upper antifuse electrode.

Method of fabricating an antifuse

A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Circuits for ESD Protection of metal to-metal antifuses during processing

Dielectric-polysilicon-dielectric antifuse for field programmable logic

The present invention is directed to providing an electrostatic discharge ('ESD') protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells. Where the antifuse material layer is an O--N--O sandwich, the top oxide and nitride layers may be etching during the block etching process leaving the thin bottom oxide layer and some or no residual bottom oxide of the ONO composite antifuse material layer for forming the ESD protection cell. Since etching into the bottom oxide of the ONO composite antifuse material layer will not degrade, but will enhance the ESD protection capability of the ESD protection cell, it is perfectly acceptable to also etch the bottom oxide layer as well as long as proper process control is allowed. The ESD protection cell may be used with antifuses having diffusion or polysilicon type bottom electrodes and polysilicon top electrodes. An advantage of this structure is its ability to be fabricated at high temperature for improved film characteristics and reliability.

Method for forming an ESD protection device for antifuses with top

Process of making ESD protection devices for use with antifuses

The present invention is directed to an antifuse structure and fabrication process wherein the bottom oxide of the ONO antifuse material layer is grown over a small area of N- diffusion surrounded by an N+ diffusion area where the N- diffusion could be patterned as N- 'islands' or as N- 'stripes', or the like, with the active N- area controlled by the formation and drive-in of the N+ diffusion layer. In this way, the bottom oxide layer of the ONO antifuse material layer is thinner at its center (above the N- region) than at its edges because oxide grows slower on the less doped N- region at the center of the antifuse than at the more heavily doped N+ regions at the edges of the antifuse. Forcing the center of the antifuse material layer to be thinner causes the antifuse to preferentially break down at its center and away from its edges. The opening in the antifuse cell opening mask is wider than the width of the N- diffusion area so that both N- and N+ areas are exposed in the antifuse cell opening step. Since the N+ diffusion can be very accurately dimensionally controlled with known techniques, it is thus possible to reduce the dimension of the active N- diffusion down to 0.2 .mu.m or below, comparing favorably with the linear dimension of 1.0 .mu.m used in currently available state-of-the-art manufacturing processes for antifuses. This represents a factor of 25 reduction in the active antifuse area, which in turn can dramatically reduce the defect density of antifuses over current technology and/or dramatically increase the number of antifuses that may be disposed in a given area of silicon.

Edgeless, self-aligned, differential oxidation enhanced and

ESD protection device for antifuses with top polysilicon electrode

According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via. Thus the partially etched second a-Si layer forms a part of the second metallization layer and the Nitride/a-Si/Nitride insulating antifuse layer has a constant thickness determined by the process used to lay it down, rather than on the more uncontrollable etch process. Accordingly, the programming voltage of the antifuse is more predictable than with prior art antifuse structures.

Metal-to-metal antifuse including etch stop layer

Circuits for ESD protection of metal-to-metal antifuses during processing

A process electrostatic discharge ('ESD') protection device is incorporated on a chip with the antifuses that it is designed to protect and is formed as close in time as possible to the deposition of the antifuse material layer (the layer being protected) so that ESD protection is available at all practical stages of processing. According to a first aspect of the invention, an ESD protection device is formed by exposing edges of an antifuse bottom electrode during the antifuse cell open mask/etch step, It is biased on during processing. A sharp corner of the electrode and a deep aspect ratio provide degrade antifuse performance for the protection cell (resulting in reduced breakdown voltage and increased leakage current) and, as designed, the protection cell will rupture before other cells because it has a lower breakdown voltage. Once the protection cell ruptures, it will continue to conduct and protect other antifuses from ESD damage. When processing is complete, the protection cell is biased off and has no effect on the remaining antifuses. According to a second aspect of the present invention, a deep valley topography is created under a bottom electrode of the protection cell. Because the cell is deeper than the other antifuse cells while retaining the same cell opening size, the step coverage within the protection cell will be reduced and the protection cell will have a lower breakdown voltage than the regular antifuse cells formed with it. In all other respects, it operates as set forth regarding the first aspect of the invention.

A 'read-disturb' resistant metal-to-metal antifuse includes a lower electrode comprising a first metal layer in a microcircuit structure. An inter-metal dielectric is disposed over the lower electrode and includes an antifuse aperture disposed therein. A first layer of antifuse material is disposed over exposed surface of the lower electrode in the antifuse aperture. A highly conductive layer is disposed over the first region of antifuse material and a second layer of antifuse material is disposed over the highly conductive layer. An upper electrode comprises a second metal layer disposed over the second layer of antifuse material. The first and second layers of antifuse material may comprise single-layer or multi-layer dielectric materials, amorphous silicon, or combinations of these materials. A process for fabricating a read-disturb resistant metal-to-metal antifuse comprises the steps of forming a lower electrode comprising a portion of a first metal layer in a microcircuit structure; forming an inter-metal dielectric layer over the lower electrode; forming an antifuse aperture in the inter-metal dielectric layer to expose the upper surface of the lower electrode; forming a first layer of antifuse material over the exposed surface of the lower electrode in the antifuse aperture; forming a highly conductive layer over the first layer of antifuse material; forming a second layer of antifuse material over the highly conductive layer; and forming an upper electrode comprising a second metal layer over the second layer of antifuse material.

Growing community of inventors

Sunnyvale, CA, United States of America

Wenn-Jei Chen