Glenfly Tech Co., Ltd.

Wenlin Hao

Fengxia Wu

Yuanfeng Wang

The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix. The data process apparatus can improve the efficiency of accessing the internal memory unit and reduce the bandwidth occupied by invalid data; enable hardware pipelines to be tighter and reduce idle clock cycles; and enable the shader level-1 cache to be smaller, thereby reducing hardware costs.

Data process apparatus for to-be-cached matrix and method thereof

A graphics processing unit includes a pixel shader, an output merger, a cache, and a memory. The pixel shader is configured to output a pixel data. The output merger is coupled to the pixel shader and configured to receive the pixel data. The output merger outputs the pixel data and a sample mask corresponding to the pixel data. The cache is coupled to the output merger and configured to receive the pixel data and the sample mask. The cache generates a sample data according to the pixel data and the sample mask. The memory is coupled to the cache. The cache writes the sample data into the memory. A data size of the sample data is a multiple of a data size of the pixel data. An operation method thereof is also provided.

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Shanghai, China

Wenlin Hao