Semiconductor Manufacturing International (shanghai) Corporation

Wenjun Weng

Yan Chen

Hongwei Li

Paul Ouyang

Huijuan Cheng

Kai Zhu

Zhiguang Guo

Shanyue Mo

A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.

High-voltage-tolerant pull-up resistor circuit

An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference.

ESD protection structure and ESD protection circuit

An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal.

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Shanghai, China

Wenjun Weng