Qualcomm Incorporated

Other

Wenjun Su

Chiewcharn Narathong

Aristotele Hadjichristos

Chulkyu Lee

Le Od Zhang

Marco Cassia

Guangming Yin

Gurkanwal Singh Sahota

Seyfollah Seyfollahi Bazarjani

Louis Dominic Oliveira

Sankaran Aniruddhan

Samir Kamar Gupta

Le Zhang

Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

Serializer and deserializer for odd ratio parallel data bus

A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

Feed-forward bias circuit

Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.

Protection circuit for power amplifier

System, methods and apparatus are described that improve signaling in a three-wire multiphase communication link. A method for data communications includes determining a transition in signaling state of three wires of a communication link between a pair of consecutive symbols transmitted on the communication link, and enhancing or attenuating energy of a signal prior to the transition in signaling state of the three wires when the transition in signaling state includes a change in signaling state of a wire on which the signal is transmitted. Each symbol may define a different signaling state of the three wires of the communication link. For each symbol transmitted, two of the three wires are differentially encoded and the third wire is in a neutral state. Different wires are differentially encoded during transmission of consecutive symbols.

Programmable pre-emphasis circuit for MIPI C-PHY

Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

Multi-cascode amplifier bias techniques

Exemplary embodiment are directed to preserving transmitter linearity in RF transceivers while reducing RX band noise for use with low-power voltage supplies. In one aspect, a programmable attenuation element may be provided on-chip at the output of a driver amplifier, prior to a matching network. In another aspect, the programmable attenuation element may include a plurality of switchable capacitors.

Techniques for improving transmitter performance

A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.

High linear fast peak detector

Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.

Amplifier with gain expansion stage

A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.

Multi-modulus divider retiming circuit

Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.

Versatile and compact DC-coupled CML buffer

A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.

Low-power modulus divider stage

Within a mobile communication device (for example, a cellular telephone), there is a local oscillator. The local oscillator includes a novel frequency divider that includes a novel configurable multi-modulus divider (CMMD). The frequency divider is configurable into a selectable one of multiple configurations involving different mixes of synchronous and asynchronous circuitry. In each configuration, the frequency divider produces an amount of noise and consumes an amount of power. Power consumption is loosely inversely related to noise produced in that the modes with the highest power consumption produce the least amount of noise, and vice versa. The mobile communication device is operable in one of multiple different communication standards (for example, GSM, CDMA1X and WCDMA). The different communication standards impose different noise requirements on the frequency divider. By using the lowest power configuration that satisfies the noise requirements of the standard being used, power consumption of the cellular telephone is reduced.

Configurable multi-modulus frequency divider for multi-mode mobile communication devices

A wireless communication device () may include a receiver (), a memory (), a digital-to-analog converter (), an audio playback system () and other features. A dynamic range controller () selectively generates control signals to adjust, at least in part, the operational dynamic range of the digital-to-analog converter () for digital signals received by the receiver () or stored in the memory (). The selection of dynamic range is based on identifying a characteristic. In one embodiment, the control signals are used to selectively operate the digital-to-analog converter () at a particular dynamic range based on a sampling rate of a received digital audio signal.

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San Diego, CA, United States of America

Wenjun Su