Intel Corporation

Wenhui Shu

Andrew J Herdrich

Qian Li

Xiang Sean Zhou

Xiaoguo Liang

Ian M Steiner

Rameshkumar G Illikkal

Slawomir Putyrski

Nikhil Gupta

Ripan Das

Haifeng Gong

Alexander B Uan-Zo-li

Chuan Song

Teck Joo Goh

Andrzej Kuriata

Daniel Richins

Long Cui

Jinshi Chen

Dharmisha Ketankumar Doshi

Mihai Daniel Dodan

Dianjun Sun

Shruthi Venugopal

Anna Drewek-Ossowicka

Mihai-Daniel Dodan

Sixiao Huo

Various approaches to efficiently allocating and utilizing hardware resources in data centers while maintaining compliance with a service level objective (SLO) specified for a computational workload is translated into a hardware-level SLO to facilitate direct enforcement by the hardware processor, e.g., using a feedback control loop or model-based mapping of the hardware-level SLO to allocations of microarchitecture resources of the processor. In some embodiments, a computational model of the hardware behavior under resource contention is used to predict the application performance (e.g., as measured in terms of the hardware-level SLO) to be expected under certain contention scenarios. Scheduling of workloads among the compute nodes within the data center may be based on such predictions. In further embodiments, configurations of microservices are optimized to minimize hardware resources while meeting a specified performance goal.

Efficient resource allocation for service level compliance

Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

Dynamic control of memory bandwidth allocation for a processor

In some examples, a control unit is configured to control a computer server rack having a first grid power source, a second grid power source, and a battery backup system. The control unit is adapted to monitor a failed status of one or more power supply units in the computer server rack, to determine location information relating to the one or more power supply units having the failed status, to determine input power of the one or more power supply units having the failed status, to adjust an input power of the first grid power source based on the determined input power, and to adjust an input power of the second grid power source based on the determined input power.

Limiting computing rack input power due to power supply unit failure

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Shanghai, China

Wenhui Shu