Advanced Micro Devices Corporation

Other

Spansion Llc.

Weng Fook Lee

Edward V Bautista, Jr

Ken Cheong Cheah

Santosh K Yachareni

Feng Q Pan

Darlene G Hamilton

Colin Stewart Bill

Boon Tang Teh

Kazuhiro Kurihara

Pau-Ling Chen

Ravi S Sunkavalli

Keith H Wong

Joseph Kucera

Azrul Halim

Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.

Method and apparatus for pre-charging negative pump MOS regulation capacitors

An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

Address sequencer within BIST (Built-in-Self-Test) system

A method for erasing a flash memory. In a flash memory device having multiple sectors a plurality of sectors is selected for erase (). a subset of sectors is selected () and an erase pulse is applied simultaneously to all sectors in the subset (). After the application of an erase pulse having an initial voltage value, at least one sector of the subset is verified (). If there is at least one unerased cell in the verified sector, the erase voltage is adjusted () and another erase pulse is applied to the subset of sectors (). The adjustment of the erase voltage may be a function of the number of times that an erase pulse has been applied to the subset. This cycle is repeated on the subset until the selected sector is verified as erased. After a sector is verified, the erase/verify cycle is applied to one or more of the remaining sectors in the subset until each of the remaining sectors has been verified as erased. After all of the sectors in the subset are erased, the erase voltage is reset to its initial value () and another subset of sectors is selected for erase/verify as described above (). The process may be repeated until all of the memory sectors in the device have been erased (). A flash memory device with embedded logic may be used to execute the method.

System and method for erase voltage control during multiple sector erase of a flash memory device

A method of implementing a reference current measurement mode within a reference array programming mode or a reference array erase mode in a semiconductor chip is disclosed. This implementation leads to significant reduction in testing time for the semiconductor chip, increasing production volume and revenues.

Implementing reference current measurement mode within reference array programming mode or reference array erase mode in a semiconductor

In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode

A bus protocol is checked automatically during design or manufacture by connecting a bus protocol monitor to the bus and monitoring signals applied to the bus. The response to those signals is then compared with a predetermined desired response. A signal is generated to alert the protocol designer or manufacturing controller if there is an improper response that indicates that the protocol is in error. The invention is particularly useful as applied to check an LPC bus protocol.

Real time automated checking mechanism for a bus protocol on an integrated bus system

There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.

Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling

A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

System and method to facilitate stabilization of reference voltage signals in memory devices

Adder circuitry is provided based on a reduced mathematical method to provide high-speed hexadecimal addition. A first adder adds the least significant binary digits of two hexadecimal numbers to provide a Digit and a Dot , and a second adder adds the second least significant binary digits to provide a Digit plus a Dot as a Sum and a CarryA. A secondary adder adds the Dot and the Sum to provide the sum of Digit plus Dot and Dot as a SumA. A generator generates a Dot of hexadecimal &ldquo;1&rdquo; for certain values of the Sum and the CarryA, and a detector triggers an output device, which outputs a hexadecimal &ldquo;0&rdquo;, to output the Dot in response to a certain pattern of hexadcecimal numbers in the Dot and the Sum . Thus, the least signifigant digit of the added hexadecimal numbers is Digit , the second least significant digit is SumA, and the third least significant digit is the output of the output device.

High-speed hexadecimal adding method and system

Methods and apparatus are disclosed for verifying soft programming of one or more memory cells in a memory device. The methods comprise providing a voltage source to the core cell gate, and verifying soft programming of the cell after overshoot in the regulated voltage source has settled. Also disclosed are memory devices having a logic circuit providing a regulated voltage source to the cell gate during a soft program verify operation, and a sensor to verify soft programming of the cell when a first voltage is applied to the gate from the regulated voltage source. The logic circuit provides a soft program verify signal to the sensor to verify soft programming after overshoot in the voltage source has settled.

Method and apparatus for soft program verification in a memory device

A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

I/O partitioning system and methodology to reduce band-to-band tunneling current during erase

A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

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Penang, Malaysia

Weng Fook Lee