Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Wendy Yu

Liang Li

Kevin Hu

Troy Guan

In a word line leakage detection process in a NAND or other non-volatile memory device, a stress selected set of word lines have a high stress voltage applied while other parts of an array are biased to a low level. While stressing the memory array, the current drawn by the array is compared to a leakage detection current that increases in amplitude. For example, this can be done by mirroring the array current and comparing this with the current from a current source that increases in response to a digital input value and determining when it exceeds the mirror current, at which point the stress is discontinued. In addition to determining the amount of leakage, this approach results in low leakage word lines receiving less stress, while greater leakage result in greater amounts of stress being applied.

Adaptive word line stress for leak detection in non-volatile memory

An apparatus for detecting the presence of assembly related defects on a semiconductor device including an edge ring having a resistance value and including one or more layers configured to at least partially cover the semiconductor device in a first direction. The one or more layers are divided into a first section and a second section. Each layer of the one or more layers are in electrical communication with one another. The resistance value of the edge ring is at a first resistance value associated with the first and second sections being intact. At least one of the first section and second section is configured to break in response to an assembly related defect, and the resistance value of the edge ring is configured to change from the first resistance value to a second resistance value in response to at least one of the first and second sections being broken.

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Shanghai, China

Wendy Yu