Motorola Corporation

Wendy Reed

Hing Leung Yiu

Glen James Zoerner

Ralph E Snowden

Harvey H Wong

Wai-Kin Steven Kwan

On Ki Chu

A method and apparatus for reducing power consumption in a portable electronic device (100) with an LCD screen (104) and operating with a CPU (114) switchable between a high power mode and a low power mode. When input commences on a surface of the LCD screen (104), an interrupt signaler (108) generates a first interrupt signal to an interrupt controller (112). Upon receiving the first interrupt signal, the interrupt controller (112) switches the CPU (114) from the low power mode to the high power mode, turning on at least one detection panel (106) coupled to the LCD screen (104) and to an ADC (110). When input ceases on the surface, the interrupt signaler (108) generates a second interrupt signal to switch the CPU (114) from the high power mode to the low power mode, turning off the at least one detection panel (106) and the ADC (110).

Method for reducing power consumption in a portable electronic device

When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

Circuit and method for retaining data in DRAM in a portable electronic

A data processing system (10) including a chip select circuit (40) which allows flexible attribute protection, and a method for providing a plurality of chip select signals in the data processing system are disclosed. Each of two or more decoders (42, 48) determines whether a bus cycle address is within a programmable region and matches one or more programmable attributes, and if so activates a corresponding match signal. A logical operation circuit (60) then selectively causes a chip select signal (72) to be activated in response to a logical operation performed on the match signals. In one embodiment, the logical operation circuit (60) may cause the chip select signal (72) to be activated if either of two match signals (47, 53) is activated, allowing for example the same region of memory to be accessed from two address spaces using the same chip select signal (72).

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Austin, TX, United States of America

Wendy Reed