Arm Limited

Cadence Design Systems, Inc.

Wendy Arnott Elsasser

Stephan Diestelhorst

Prakash Shyamlal Ramrakhyani

Wei Wang

Jonathan Curtis Beard

Nikos Nikoleris

Andreas Hansson

Yew Keong Chong

George McNeil Lattimore

Mudit Bhargava

Ali Ghassan Saidi

Eric Van Hensbergen

Andreas Lars Sandberg

Roberto Avanzi

Michael Andrew Campbell

Joel Thornton Irby

James Dennis Dodrill

Joshua Randall

Kshitij Sudan

Marc Greenberg

Andrea Pellegrini

Jiajun Wang

Gururaj Saileshwar

Shibo Wang

A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

Non-volatile memory on chip

Disclosed are devices, method and/or systems for responding to a request for accessing a portion of a memory prior to completion of a requested operation to place the portion of the memory in an initialized state. In one example implementation, a memory controller may delay initiation of a write operation addressed to a particular portion of the memory until completion of a pending request to initialize the particular portion of the memory. In another example implementation, a memory controller may return values to service a request for a read operation comprising values representing an initialized state without accessing the particular portion of the memory responsive to a presence of a pending request to initialize the particular portion of the memory.

Initialisation of a storage device

A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.

Method and apparatus for control of a tiered memory system

Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

Storage circuitry responsive to a tag-matching command

Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in response to a memory instruction from a cache client. The cache monitor includes a predictor table and update logic. An entry in the predictor table comprises an instruction identifier that associates the entry with a memory instruction and, for each cache in the system, a reuse counter. The update logic is configured to update a reuse counter table dependent upon cache behavior in response to memory instructions. Storage of data a first data address in cache in response to a memory instruction having a first instruction identifier, is dependent upon reuse counter values in an entry of the predictor table associated with first instruction identifier. Reuse counters are updated dependent upon cache behavior. A Bloom filter or other data structure may be used to associate data addresses with a memory instruction.

Multi-tier cache placement mechanism

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

Method and apparatus for maintaining data coherence in a non-uniform compute device

A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.

Counter integrity tree for memory security

An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.

Apparatus and method of handling caching of persistent data

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

Method and apparatus for scheduling in a non-uniform compute device

A method and apparatus for retrieving data from a memory in which data, an associated message authentication code (MAC) and an associated error correction code (ECC) are stored in a memory such that the data, MAC and ECC can be retrieved together in a single read transaction and written in a single write transaction. Additional read transactions may be used to retrieve counters values that enable the retrieved MAC to be compared with a computed MAC. Still further, node value values of an integrity tree may also be retrieved to enable hash values of the integrity tree to be verified. The MAC and ECC may be stored in a metadata region of a memory module, for example.

Memory organization for security and reliability

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.

Method and apparatus for reordering in a non-uniform compute device

A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.

Method and apparatus for hardware management of multiple memory pools

An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands

A method and system for re-ordering bits in a memory system is disclosed. The memory system includes a system on a chip (SoC) coupled to a plurality of memory chips. Each of the memory chips including a memory array, multipurpose registers (MPRs) coupled to the memory array; and a data bus coupled between the SoC and the memory array. The method and system comprise utilizing the MPRs within each of the plurality of memory chips to determine bit ordering within each byte lane of memory array of the associated memory chip. The method and system further includes providing the determined bit ordering to the SoC.

Growing community of inventors

Austin, TX, United States of America

Wendy Arnott Elsasser