Micron Technology Incorporated

International Business Machines Corporation

Other

Siemens Corporation

Micro Technology, Inc.

Mircon Technology, Inc.

Micron Tecnology, Inc.

Wendell P Noble

Leonard Forbes

Kie Y Ahn

Eugene H Cloud

Alan R Reinberg

David V Horak

Mark Charles Hakey

William H Ma

Steven J Holmes

Paul A Farrar

Gary Bela Bronner

Badih El-Kareh

Ashwin K Ghatalia

Wilfried Hansch

Jack Allan Mandelman

Roy E Scheuerlein

John Atkinson Fifield

Wilbur David Pricer

John Kenneth DeBrosse

Paul Christian Parries

John E Gersbach

William Warren Walker

Harish N Kotecha

Rick L Mohler

Mousa H Ishaq

Francis W Wiedman, Iii

Richard Alan Unis

Dale L Critchlow

A DRAM array having trench capacitor cells of potentially 4Fsurface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Trench DRAM cell with vertical device and buried word lines

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the &#x3c;110&#x3e; direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the &#x3c;110&#x3e; direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Method and apparatus on (110) surfaces of silicon structures with conduction in the &#x3c;110&#x3e; direction

Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiOon a top surface of a silicon wafer and a trench layer of SiOon a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

Multiple oxide thicknesses for merged memory and logic applications

In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions. In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.

Methods of forming interconnect lines

A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures

Methods of forming electrical connections

High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

High density SRAM cell with latched vertical transistors

Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry

A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the p-channel transistor is coupled to a second source/drain region of the MOSFET which serves as the gate for the JFET. The second source/drain region of the MOSFET is additionally coupled to a charge storage node. Together the second source/drain region and charge storage node provide a bias to the body of the JFET that varies as a function of the data stored by the memory cell. A non destructive read operation is achieved. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the JFET so that the JFET has a first turn-on threshold for a stored logic '1' condition and a second turn-on threshold for a stored logic '0' condition. The charge storage node is a plate capacitor which surrounds the second source/drain region of the MOSFET. The vertical gain cell is fabricated so that the write word line, read bit line, read word line and capacitor are buried beneath the silicon surface. As a result the cell can be fabricated in an area as small as four (4) lithographic feature squares.

Vertical gain cell and array for a dynamic random access memory and method for forming the same

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

DRAM technology compatible processor/memory chips

Growing community of inventors

Milton, VT, United States of America

Wendell P Noble