Dallas Semiconductor Corporation

Motorola Corporation

Other

Dallas Semiconducter Corp.

Wendell L Little

Stephen N Grider

Michael L Bolan

Andreas Curiger

Stephen M Curry

David A Bunsey

Bradley M Harrington

James E Bartling

Shyun Liu

Joseph Wayne Triece

Walter L Davis

Barry W Herold

Matthew K Adams

Don Folkes

Kenneth R Burch

Kevin E Deierling

Donald W Loomis

Michael D Smith

Francis A Scherpenberg

Edward Tangkwai Ma

Tim A Williams

William J Podkowa

Steven N Hass

Peter Schweitzer

Christopher W Fox

Mark L Thrower

Frank V Taylor, Iii

Steven N Grider

Ricky D Fieseler

Matt Adams

Steve Grider

Clark A Williams

Elaine Jansen

Bryan M Armstrong

Walter Lee Davis

The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX ) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.

Method and apparatus for 24-bit memory addressing in microcontrollers

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Parasitically powered microprocessor capable of transmitting data over a single data line and ground

An integrated circuit, such as a microprocessor, which incorporates hardware mechanisms to prevent the circuitry from operating outside the proper bounds of design. The hardware circuitry prevents the microprocessor circuitry from being forced to operate at clock speeds that are greater than it is designed for, from operating at temperatures above or below that which it is designed for, and from being forced to operate at voltages that are above or below voltages that the microprocessor is designed to operate at.

Integrated circuit having hardware circuitry to prevent electrical or thermal stressing of the silicon circuitry

A microcontroller communicating via a data path and an address path with a memory block containing encrypted contents, the microcontroller including the capability for detecting resets effectuated in the wake of an unauthorized attempt to gain access to the encrypted contents and the capability of evading such an unauthorized attempt.

Systems and methods for protecting access to encrypted information

An 8051 microprocessor core having an ability to operate via an external crystal oscillator or be switched to operate in a low power mode via an internal ring oscillator.

Microcontroller with selectable oscillator source

Microprocessor with coprocessing capabilities for secure transactions and quick clearing capabilities

An improved clocking system for micro controllers is provided. The micro controller has two mechanisms by which the clocking is provided. One clock is provided by an external clock signal which is generally crystal controlled. A second mechanism for providing the clock is also present. This second clock can be useful as the 'primary' or first clock which is generally a crystal oscillator may take several milliseconds to stabilize following a restart from a stop mode. The second clock mechanism can for example be an internal ring oscillator or other type of clock which although not as accurate as a crystal clock does not require the several milliseconds to recover.

Clocking system for microcontrollers

Circuitry which performs modular mathematics to solve the equation C=M.sup.k mod n and n is performed in a manner to mask the exponent k's signature from timing or power monitoring attacks. The modular exponentation function is performed in a normalized manner such that binary ones and zeros in the exponent are calculated by being modulo-squared and modulo-multiplied.

Method and apparatus for masking modulo exponentiation calculations in

A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.

Microcontroller having register direct and register indirect addressing

A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.

Current compensated clock for a microcircuit

A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that may be produced by a pre-specified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.

Microcircuit with memory that is protected by both hardware and software

In a data bus environment where a host device and a plurality of other devices are connected to the bus, the time required for the first and the last device to respond to a host request is measured. Once the time required between the first and the last response is known, then a read/write window time can be minimized thereby increasing the speed of communication over the data bus.

Method and system for measuring a maximum and minimum response time of a

A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. Another of the innovative teachings set forth in the present application is that the microprocessor can access the auxiliary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxiliary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, and detects that the power supply voltage is still marginal, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal so that the microprocessor does not go into full operation until the supply voltage is high enough.

Integrated circuit for providing supervisory functions to a

A processor system is disclosed wherein said processor system is adapted to communicate over at least one one-wire network utilizing one-wire communications protocol. For the embodiment of the invention in which the processor system acts as a network master, the processor system includes a master UART especially configured to control communications over such network according to one-wire protocol. For the embodiment of the invention in which the processor communicates over two one-wire networks, the processor system includes a first UART which acts as a slave and a second UART which acts as a master.

Universal asynchronous receiver/transmitter (UART) slave device

Growing community of inventors

Denton, TX, United States of America

Wendell L Little