Texas Instruments Corporation

Halo Microelectronics International

Wenchao Qu

Zhao Fang

Gangqiang Zhang

Anuj Jain

Eung Jung Kim

Md Abidur Rahman

Sudhir Nagaraj

Michael Edwin Butenhoff

Yang Xu

Tianhong Yang

Ryan Paul Kehr

Mario Marascutti

Muhammad Ahmed

Cameron Wayne Phillips

Kuangyu Chiang

An apparatus includes a first switch and a second switch connected in series between an input voltage bus and ground, a bootstrap capacitor connected between a bootstrap voltage bus, and a common node of the first switch and the second switch, and a bias power control circuit configured to function as a switched capacitor bootstrap circuit when the apparatus is configured to operate in a high impedance PFM mode, and configured to function as an active bootstrap circuit when the apparatus is configured to operate in another operating mode.

Bootstrap apparatus and control method

An apparatus includes an enable circuit having a first input configured to receive a serial data in (SDI) signal, a second input configured to receive a not chip select (nCS) signal, a third input configured to receive a hold (HLD) signal, and an output configured to generate an internal enable signal for controlling a power-up process and a power-down process of an integrated circuit, and a digital core circuit configured to generate the HLD signal after the integrated circuit is powered up by the SDI signal and the nCS signal.

Integrated circuit control apparatus and method

In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.

Short circuit protection

A low dropout regulator includes a first transistor having a first drain/source terminal coupled to an input terminal of a regulator, and a second drain/source terminal coupled to an output terminal of the regulator, a second transistor having a first drain/source terminal coupled to the input terminal of the regulator, and a second drain/source terminal coupled to the output terminal of the regulator through a resistor, and an error amplifier having an inverting input configured to receive a reference, a non-inverting input configured to detect an output voltage of the regulator, and an output coupled to gates of the first transistor and the second transistor.

Low dropout regulator and control method

An ESD protection apparatus includes a discharge resistor and a transistor connected in series between a first voltage rail and a second voltage rail, a first coupling capacitor, a diode and a first bias resistor connected in series between the first voltage rail and the second voltage rail, wherein a common node of the diode and the first bias resistor is connected to a gate of the transistor, and an ESD protection device connected between the first voltage rail and the second voltage rail.

ESD protection apparatus and control method

A signal processing apparatus includes a signal processing circuit configured to process a signal obtained from a voltage bus, a high voltage circuit configured to withstand a voltage stress when a high voltage is applied to the voltage bus, and a bypass circuit configured to bypass the high voltage circuit when a low voltage is applied to the voltage bus.

Signal processing apparatus and control method

An apparatus includes a first diode and a second diode connected in series between a first voltage terminal and a second voltage terminal, a switch connected between the first voltage terminal and the second voltage terminal, and a clamping threshold circuit connected between a common node of the first diode and the second diode, and a gate of the switch, wherein the clamping threshold circuit is configured such that in response to a voltage surge applied to the common node of the first diode and the second diode, the switch is turned on once the voltage surge is greater than a predetermined threshold.

Surge protection apparatus

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

Fault voltage scaling on load switch current sense

Stepper motor winding current regulation methods and apparatus adapt a maximum blanking period to generate an adapted blanking period that is proportional to a currently-selected current regulation set-point. Sensed winding current feedback is ignored at a current regulation controller during the adapted blanking period or during a minimum blanking period, whichever longer, to avoid attempting to track noise imposed upon a sensed winding current feedback signal at an initiation of rapid current changes di/dt. Doing so may decrease ripple in the motor winding current waveform and reduce zero-crossing distortion by decreasing overshoot of the current regulation set-point by the sensed winding current.

Sensed motor winding current adapting blanking period between max/min values

Stepper motor winding current regulation methods and apparatus continuously and bi-directionally sense winding current to determine both the magnitude of the winding current and the slope of a waveform representing the winding current. The magnitude and slope information is used to more precisely control periods of current rise and characteristics of fast and slow current decay during pulse-width modulation ('PWM') regulation cycles. Winding current rise and decay shaping is based upon the sensed magnitude of the winding current, the magnitude of the winding current regulation set-point ITRIP, whether the sensed winding current is greater than or less than ITRIP at a selected sampling time, whether the sensed winding current is increasing or decreasing when a waveform of the sensed winding current crosses over ITRIP, and whether or not the magnitude of ITRIP changes during a PWM cycle in response to a receipt of a subsequent DAC code.

Dynamic mixed-mode current decay apparatus and methods

Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

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Dallas, TX, United States of America

Wenchao Qu