Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company, Limiied

Wenchao Hao

Ching-Wei Wu

He-Zhou Wan

XiuLi Yang

Kuan Cheng

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

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Shanghai, China

Wenchao Hao