Shenzhen Microbt Electronics Technology Co., Ltd.

Wenbo Tian

Zuoxing Yang

Zhijun Fan

Haifeng Guo

Weixin Kong

Dong Hai Yu

Chuan Gong

Nan Li

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

D flip-flop having multiplexer function

A dynamic D flip-flop with an inverted output involves an input end () used for receiving input data; an output end () used for providing output data to respond to the input data; a clock signal end () used for receiving a clock signal; a first latch () used for latching the input data from the input end () and performing inverting transmission on the input data under the control of the clock signal; a second latch () used for latching data from the first latch () and performing inverting transmission on the data latched by the first latch () under the control of the clock signal; and an inverter () used for performing inverting output on the data received from the second latch (), the first latch (), the second latch (), and the inverter () being sequentially connected in series between the input end and the output end.

Dynamic D flip-flop with an inverted output

A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

D flip-flop, processor including the d flip-flop, and computing apparatus

The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Latch, processor including latch, and computing apparatus

The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Chips placed in full-custom layout and electronic device for implementing mining algorithm

The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal. A source of the first NMOS transistor is configured to receive the first output signal, and a gate is configured to receive the third input signal. The simple logic gate circuit is an AND or OR gate circuit, and the first logic gate circuit is a NAND or NOR gate circuit.

Composite logic gate circuit

A standard unit () for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit () includes a first transistor () of a first threshold type and a second transistor () of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Growing community of inventors

Guangdong, China

Wenbo Tian