Macdermid Enthone Gmbh

Wenbo Shao

Vincent Paneccasio, Jr

Thomas B Richardson

Joseph Anthony Abys

Richard W Hurtubise

Eric Yakobson

Elie H Najjar

Shaopeng Sun

Cai Wang

Chen Wang

Xuan Lin

Theodore Antonellis

Taylor L Wilkins

Yun Zhang

Kyle M Whitten

Sean Xuan Lin

Jr Vincent Paneccasio

A nickel electrodeposition composition for via fill or barrier nickel interconnect fabrication comprising: (a) a source of nickel ions; (b) one or more polarizing additives; and (c) one or more depolarizing additives. The nickel electrodeposition composition may include various additives, including suitable acids, surfactants, buffers, and/or stress modifiers to produce bottom-up filling of vias and trenches.

Composition and method for fabrication of nickel interconnects

A method of forming a diffusion barrier layer on a dielectric or semiconductor substrate by a wet process. The method includes the steps of treating the dielectric or semiconductor substrate with an aqueous pretreatment solution comprising one or more adsorption promoting ingredients capable of preparing the substrate for deposition of the diffusion barrier layer thereon; and contacting the treated dielectric or semiconductor substrate with a deposition solution comprising manganese compounds and an inorganic pH buffer (optionally, with one or more doping metals) to the diffusion barrier layer thereon, wherein the diffusion barrier layer comprises manganese oxide. Also included is a two-part kit for treating a dielectric or semiconductor substrate to form a diffusion barrier layer thereon.

Method and wet chemical compositions for diffusion barrier formation

A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Process for filling vias in the microelectronics

A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature. The deposition composition comprises (a) a source of copper ions; (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof; (c) an organic disulfide compound; (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof; and (d) chloride ions.

Copper filling of through silicon vias

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Milford, CT, United States of America

Wenbo Shao