Microsemi Semiconductor Ulc

Zarlink Semiconductor Limited

Wenbao Wang

Gabriel Rusaneanu

Krste Mitric

Qu Gary Jin

Simon John Skierszkan

Slobodan Milijevic

Paul H L M Schram

Mark A Warriner

Cathy Zhang

Kwok Fai Chan

A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).

PLL system with master and slave devices

A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.

Method for improving the performance of synchronous serial interfaces

In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Hardware delay compensation in digital phase locked loop

A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Frame boundary discriminator

A virtual counter for dynamically calculating memory addresses at a digital switch that receives data streams of different data rates. The switch has a memory that is divisible into partitions with each partition being divisible into multiple locations. A virtual counter is implemented for each data stream in a rate conversion architecture at the switch to optimize usage of the switch memory. An input virtual counter is used to calculate a data memory address and an output virtual counter is used to calculate a connection memory address.

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Wenbao Wang