Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Wen Zhi Gao

Zhao Lun

Huang Liu

Liang Choo Hsia

James Yong Meng Lee

Chung Woh Lai

Johnny Widodo

Shailendra Mishra

Shiang Yang Ong

Fang Chen

Yew Tuck Chow

Hong Yu

Jianwei Peng

Hsien-Ching Lo

Tao Han

Shiv Kumar Mishra

Byoung-Gi Min

Aditya Kumar

Jean-Baptiste Jacques Laloë

Basab Banerjee

Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.

Double barrier layer sets for contacts in semiconductor device

A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Multi-layer spacer used in finFET

A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Method of forming shallow trench isolation structures for integrated circuits

A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rof transistors in iso and nested regions can be matched.

Nested and isolated transistors with reduced impedance difference

Growing community of inventors

Singapore, Singapore

Wen Zhi Gao