Industrial Technology Research Institute

Mediatek Corporation

Wen-Zen Shen

Hong-Ching Chen

Der-Tsuey Shen Wang, Legal Representative

Won-Yih Lin

Yea-Yun Yang

Chi-Chih Lee

I-Hau Yeh

Ye-O You

Chong-Ching Chen

An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

ACS circuit and Viterbi decoder with the circuit

A modified three-pixel antialiasing method wherein the closest pixel from a displayed line has a constant display intensity includes the steps of locating a first pixel having a shortest distance along an axis of the pixel matrix array from the line, determining the shortest distance, calculating pixel intensity for the first pixel by multiplying a maximum intensity of the first pixel with a constant value, locating a second pixel having a second shortest distance along the axis from the line, locating a third pixel having a third shortest distance along the axis from the line, calculating pixel intensity for the second pixel, and calculating pixel intensity for the third pixel.

Method for antialiasing

A multiplication device is provided for forming the product of a first and a second N-bit input binary number. The multiplication device receives the two input binary numbers and forms a two's complement product expressed in a product sum and a product carry term. The product sum and product carry terms are formed by providing an offset generation means which generates a numerical binary offset of the value determined by X=(4-2.sup.-(n-1)) and a partial product generating means which generates first and second sets of partial products. An addition means adds the offset value and first and second sets of partial products are added to form the resultant product sum and product carry terms. The product sum and product carry terms are conveyed to a second addition means wherein they are added to form a two's complement product result. Preferably the multiplication device is provided with an accumulation means to form the sum of the products of all successive pairs of input binary numbers. In this manner, the second addition means also receives from a holding means an accumulation of previously formed products in two's complement form and adds the accumulation of products, the product sum and the product carry terms to form a new two's complement accumulation of products. The new accumulation of products is conveyed to the holding means where it replaces the old accumulation of products.

Multiplication and accumulation device

Growing community of inventors

Hsinchu, Taiwan

Wen-Zen Shen