Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Wen-Yun Wang

Ching-Yu Chang

Hua-Tai Lin

Chia-Chu Liu

Yu-Chung Su

Cheng-Han Wu

Kuo-Chang Kau

Yen-Chun Chen

Hsuen-Li Chen

Po-Ting Yeh

Kuan-Sheng Lai

Chang-Jen Chen

A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.

Dual critical dimension patterning

A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.

Method for calibrating alignment of wafer and lithography system

A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Method for manufacturing semiconductor device and system for performing the same

Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 &#x3bc;m after creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

Methods for forming a stress-relieved film stack by applying cutting patterns

A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.

Anti-reflective layer and method

A method of forming a coating, comprises applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the first coating after planarizing the top surface. The first coating may be applied over the plurality of topographical features, and may be substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating. A solvent may be applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The first coating may have a planar surface prior to drying the first coating, and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.

Method and apparatus for planarization of substrate coatings

A system and method for reducing defects in photoresist processing is provided. An embodiment comprises cleaning the photoresist after development using an alkaline environment. The alkaline environment may comprise a neutral solvent and an alkaline developer. The alkaline environment will modify the attraction between residue leftover from development and a surface of the photoresist such that the surfaces repel each other, making the removal of the residue easier. By removing more residue, there will be fewer defects in the photolithographic process.

Photoresist defect reduction system and method

A system and method for photoresists is provided. In an embodiment a photoresist is developed. Once developed, the photoresist is slimmed using either a direct slimming technique or an indirect slimming technique. In a direct slimming technique the slimming agent is either an alkaline solution or a polar solvent. In the indirect slimming technique a hydrophobic material is diffused into the photoresist to form a modified region and the modified region is then removed.

Photoresist system and method

The invention discloses the color photodetector with multi-primary is introduced to detect the incident light with specific wavelength regimes. Combining the surface plasma resonance effect with photodetector can be utilized to enhance the photo-responsivity of the demanded light wavelength and also can substitute the conventionally color filter and infrared cutter. In this invention, a novel integrated photo-detector that can be realized in commercial CMOS process for achieving low-cost consideration.

Growing community of inventors

Taipei, Taiwan

Wen-Yun Wang