International Business Machines Corporation

Wen-Yuan Wang

Russell C Lange

Louis L Hsu

David Meltzer

Leon L Wu

William A Klaasen

Paul J Tsang

Richard R Konian

San-Mei Ku

Shao-Fu S Chu

Samuel R Levine

John M Angiulli

Arun K Ghose

Joseph F Shephard

Daniel L Huang

A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.

CMOS voltage controlled ring oscillator

Soft error immunity of a storage cell is greatly increased by division of a storage node into at least two portions and location of those portions on opposite sides of an isolation structure, such as a well of a conductivity type opposite to that of the substrate in which transistors of the memory cell may also be formed. The isolation structure thus limits collection of charge to only one of the portions of the storage node and reduces charge collection efficiency to a level where a critical amount of charge cannot be collected in all but a statistically negligible number of cases when such charge is engendered by impingement by ionizing radiation, such as energetic alpha particles. The layout of the memory cell having this feature also advantageously provides a simplified topology for the formation of additional ports comprising word line access transistors and bit lines.

Soft error immune CMOS static RAM cell

A deep submicron transistor fabrication method that employs only optical lithography involves the formation of a relatively wide aperture using optical techniques; the formation of composite sidewalls having differential etch resistance in the aperture to define a final aperture width less than that available with conventional optical techniques; the etching of the final aperture to expose a controlled channel length; the implantation of the channel through the aperture; and the implantation of source and drain with the sidewalls protecting previously doped LDD regions in the active area.

Deep submicron transistor fabrication method

A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

Process of making BiCMOS devices having closely spaced device regions

An error correcting logic circuit for masking faults on dual redundant interconnections. Both interconnections are inmput to a NAND or AND circuit which includes pull-up resistors to a high potential. The outputs of all the NAND circuits are connected to dual redundant logic circuits, each of which has an emitter-follower output with a load resistor to ground. The outputs of the redundant logic circuits provide the redundant interconnections to other similar error correcting logic circuits.

Dual fault-masking redundancy logic circuits

A semiconductor memory produced in a unipolar technology includes a cell which has a diffusion storage capacitor with one overlying terminal being merged with a bit/sense line, the other capacitor terminal is a diffused region and is coupled through a word transfer device to a word line injector charge source held at a fixed voltage. To provide an organized array of these cells, each bit line cell includes a shared word line charge source held at a fixed voltage and formed at the surface of a semiconductor substrate. A diffusion storage capacitor also is formed at the surface of the semiconductor and spaced apart from the shared charge source. Information is written into each bit line capacitor by applying a voltage of either of two different magnitudes, representing 1 and 0 bits of information, to the respective bit line while a word selection pulse produces an inversion layer at the surface of the substrate between each bit line capacitor and its shared word line fixed voltage charge source. At the termination of the word pulse, the fixed voltage remains stored at the capacitor node. The capacitors having the larger voltage applied to the bit line terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the fixed voltage charge source with each of its respective capacitors.

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Hopewell Junction, NY, United States of America

Wen-Yuan Wang