Taiwan Semiconductor Manufacturing Comp. Ltd.

Htc Corporation

Wen-Yuan Chen

Wen-Hsing Hsieh

Zhiqiang Wu

Jon-Hsu Ho

Kuan-Lun Cheng

Chung-Wei Wu

Cheng-Yi Peng

Tsung-Hsing Yu

Bor-Zen Tien

Song-Bor Lee

Chih-Ching Wang

Lo-Chien Lee

Hsin-Ti Chueh

Jing-Lung Wu

Yi-Ju Hsu

Jenn-Wein Wu

Ken-Ichi Goto

Yi-Ming Sheu

Chun-Fu Cheng

Chih-Pin Tsao

Zhi-Qiang Wu

Kai-Hsiu Chen

Chun Chung Su

Chia-Ying Su

Chih-Yuan Chien

Chun-Chung Su

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Source/drain features with improved strain properties

A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Semiconductor device structure incorporating air gap

A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Semiconductor device having nanosheet transistor and methods of fabrication thereof

A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.

Method of manufacturing a semiconductor device and a semiconductor device

A control method, suitable for an electronic device, includes following operations. A first connection is established based on a classic Bluetooth protocol or a Bluetooth Low Energy protocol from the electronic device to a first target device. A Bluetooth identifier of the first target device acquired in the first connection is recorded. The Bluetooth identifier of the first target device is shared. The Bluetooth identifier is utilized to establish a second connection based on the classic Bluetooth protocol or the Bluetooth Low Energy protocol to the first target device. The first connection and the second connection are established based on different protocols.

Control method for bluetooth communication and bluetooth low energy communication

Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

Transistor design

A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0&#xb0; and less than 90&#xb0;.

Method of manufacturing an integrated circuit

Methods and systems for media file management are provided. A music file including music samples is provided. The music file is analyzed to calculate a gain for each music sample. At least one valley point is detected based on the gains of the respective music samples. A first and a second specific valley points are selected from the detected valley point, and respectively setting the first and second specific valley points as a start and an end of a music segmentation. Media data is generated for media files in the electronic device based on the music segmentation.

Methods and systems for media file management

Methods and systems for media file management are provided. A music file is provided. The music file is analyzed to obtain a frequency spectrum corresponding to the music file, and at least one beat point on the time line is detected for the music file based on the frequency spectrum. Media data is generated for a plurality of media files in the electronic device based on the music file and a theme defining effects or transitions between the media files, wherein the sequence of the respective effects or transitions, and the corresponding media files which are selected for the respective effects or transitions are determined according to the at least one beat point of the music file.

A multimedia processing apparatus, method, and non-transitory tangible computer readable medium thereof are provided. The multimedia processing apparatus of the present invention includes an interface and a processing unit. The interface receives an audio stream continuously, wherein the audio stream is defined with a time line. The processing unit performs the following operations every a predetermined time interval: (a) deciding a first portion of the audio stream with reference to a time instant of the time line, (b) calculating an energy of the first portion of the audio stream, and (c) calculating a difference between the energy and a previous energy. The processing unit decides a plurality of second portions of the audio stream and decides a beat point for each of the second portions by selecting the time instant that corresponds to the maximum difference within the second portion.

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Yangmei, Taiwan

Wen-Yuan Chen