Spansion LLC.

Advanced Micro Devices Corporation

Other

Cypress Semiconductor Corporation

Lumileds LLC

Monterey Research, LLC

Globalfoundries Inc.

Lumileds Holding B.v.

Wen Yu

Paul Raymond Besser

Connie Pin-Chin Wang

Fei Wang

Shenqing Fang

Jinsong Yin

Keizaburo Yoshie

Oleg Borisovich Shchekin

Connie P Wang

Andrei Papou

Minh-Van Ngo

Ashish Tandon

Robert J Chiu

Rajat Sharma

Erik William Young

Kyunghoon Min

Jeremias D Romero

Luke Gordon

Eunha Kim

Stephen B Robie

Joseph Flemish

Hiu-Yung Wong

Bhanwar Singh

Matthew S Buynoski

Steven C Avanzino

Calvin T Gabriel

Jeffrey Allan Shields

Simon S Chan

Zheng Wang

Yu-Chen Shen

Joong Jeon

Bryan K Choo

Alexander H Nickel

Kuochou Tai

Jeffrey Dellert Kmetec

Ercan Adem

David H Matsumoto

Franklin Joseph Wall

Mohiuddin Mala

Erik Wilson

Winny Stockwell

Bin Yang

Haijiang Yu

Robert Zona

A device may include a metal contact between a first isolation region and a second isolation region on a first surface of an epitaxial layer. The device may include a first sidewall and a second sidewall on a second surface of the epitaxial layer distal to the first isolation region and the second isolation region. The device may include a wavelength converting layer on the epitaxial layer between the first sidewall and the second sidewall.

Monolithic segmented LED array architecture with islanded epitaxial growth

A light-emitting device is disclosed which includes a segmented active layer disposed between a segmented conductivity layer and a continuous conductivity layer, the active layer, the segmented conductivity layer, and the continuous conductivity layer being arranged to define a plurality of pixels, each pixel including a different segment of the segmented conductivity layer and the segmented active layer. A continuous wavelength converting layer disposed on the continuous conductivity layer is provided. A plurality of first contacts, each first contact being electrically connected to a different segment of the segmented conductivity layer is provided. One or more second contacts that are electrically connected to the continuous conductivity layer are also provided, the number of second contacts being less than the number of first contacts.

Monolithic, segmented light emitting diode array

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

Memory device interconnects and method of manufacture

At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

Light emitting die () comprising a plurality of light emitting elements (310A, 310B), each having a pair of bond pads (NPand NP), wherein at least two diagonally opposite bond pads of adjacent light emitting elements on a die have their facing corners truncated () to enable a direct diagonal coupling of a complementary pair of diagonally opposite bond pads when the die is monted on a substrate on which an interconnection pattern is formed. By enabling diagonal as well as lateral coupling of the bond pads of multiple light emitting elements of a die, the multiple light emitting elements may be arranged in a variety of series and/or parallel configurations, thereby facilitating the use of the same die at different nominal operating voltages with a single interconnect layer on the substrate upon which the die is mounted.

Die bond pad design to enable different electrical configurations

The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.

Method of depositing copper using physical vapor deposition

An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

Ruthenium interconnect with high aspect ratio and method of fabrication thereof

The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50&#xb0; C. or less, with the deposition taking place at a power level of 300 W or less.

Memory device interconnects and method of manufacturing

The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Methods of forming silicides of different thicknesses on different structures

A method of forming a contact in a semiconductor device provides a titanium contact layer in a contact hole and a MOCVD-TiN barrier metal layer on the titanium contact layer. Impurities are removed from the MOCVD-TiN barrier metal layer by a plasma treatment in a nitrogen-hydrogen plasma. The time period for plasma treating the titanium nitride layer is controlled so that penetration of nitrogen into the underlying titanium contact layer is substantially prevented, preserving the titanium contact layer for subsequently forming a titanium silicide at the bottom of the contact.

Method of forming a contact in a semiconductor device with engineered plasma treatment profile of barrier metal layer

A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness.

Forming metal-semiconductor films having different thicknesses within different regions of an electronic device

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.

Semiconductor component having a contact structure and method of manufacture

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Fremont, CA, United States of America

Wen Yu