Nuvoton Technology Corporation

Winbond Electronics Corporation

Megawin Technology Co., Ltd.

Windbond Electronics Corp.

Wen-Ying Wen

Chih-Ming Chen

Erik S Jeng

Yu-Chi Chang

Chih-Hsueh Hung

Jyh-Long Horng

Bai-Jun Kuo

Chih-Hao Chen

Chih-Wei Chen

Shyh-Chyi Wong

Tung-Yi Chan

Md Imran Siddiqui

Chun Hung Peng

Tzong-Liang Chen

Han-Hui Chiu

Jyhlong Horng

A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.

High electron mobility transistor device and manufacturing method thereof

A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

High electron mobility transistor (HEMT) device having a metal nitride layer disposed between gate contact and a capping layer and a method for forming the same

A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

High voltage junction terminating structure of high voltage integrated circuit

A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.

Semiconductor apparatus

Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Semiconductor device

A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a plurality of junction gate field-effect transistors (JFETs) connected in parallel is provided. The MOSFET is disposed on a substrate. The MOSFET includes a source region, a drain region, and a gate structure disposed between the source region and the drain region. The JFETs and the MOSFET are connected in series. Each of the JFETs laterally extends between the source region and the drain region.

A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.

A method includes forming a first nitride layer on a semiconductor substrate, forming a first oxide layer on the first nitride layer, forming a first trench through the first oxide layer, the first nitride layer and a portion of the semiconductor substrate, forming a first spacer on a sidewall of the first trench, forming a second trench in the semiconductor substrate by using the first spacer as a mask, forming a third trench, forming a second oxide layer in the second trench, wherein the second oxide layer laterally extends into the semiconductor substrate and under the first spacer, forming a second spacer on a sidewall of the third trench, and removing a portion of the first nitride layer and a portion of the semiconductor substrate by etching and using the second spacer as a mask to form a fin structure on the second oxide layer.

Semiconductor devices and methods for forming the same

A reference voltage generating circuit. A bandgap circuit includes a current mirror circuit and an output circuit. The current mirror circuit generates a first current. The output circuit generates a reference current based on the first current. A compensation circuit is coupled to the bandgap circuit in parallel at a combination node and generates a compensation current. The compensation current is smaller than the reference current. The reference current has a first temperature coefficient and the compensation current has a second temperature coefficient that is inverse to the first temperature coefficient. The reference current and the compensation current are combined at the combination node, such that an absolute value of a temperature coefficient of the reference voltage of the combination node is smaller than an absolute value of the first temperature coefficient and an absolute value of the second temperature coefficient.

Reference voltage generating circuits

The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

Fabrication method for forming flash memory device provided with adjustable sharp end structure of the L-shaped floating gate

The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a semiconductor substrate to form a L-shaped poly spacer, which is so called the L-shaped floating gate. The respective inside portion of L-shaped floating gate is gibbous and to form a tip structure. Then, an isolating dielectric layer and a control gate are formed thereon. The control gate is covering the gibbous tip structure of the L-shaped floating gate to complete a flash memory device. The present invention is provided with a channel length, which is stably and easily controlled, and a tip structure for point discharging. Hence, the present invention can enhance the isolating effect between the control gate and the floating gate to achieve the purpose of repeating control the fabrication of the semiconductor devices.

Fabrication method of flash memory device with L-shaped floating gate

The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Method of forming twin-spacer gate flash device and the structure of the same

The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

Method of fabricating poly spacer gate structure

In a traditional ROM semiconductor process, ROM codes are performed by ion implantation. Due to the limitations of ion implantation energy and threshold control, the implantation for program codes must be performed before forming an inter-layer oxide layer. Therefore, the required delivery time of the process becomes longer. The invention provide a method of manufacturing ROMs that can shorten delivery time by using only one mask to simultaneously form program codes and contact windows.

Method and structure for manufacturing ROMs in a semiconductor process

An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Growing community of inventors

Hsinchu, Taiwan

Wen-Ying Wen