Huawei Technologies Co., Limited

Wen Yin

Wei Li

Xu Zhang

Hong Li

Kun Zhang

Yigang Zhou

Ruonan Wang

Yining Li

Manbo Wu

Xianzhou Lin

Xiaowei Lin

Chuanwei Wen

Yuwei Li

Yingxin Qiu

A field effect transistor and a preparation method thereof, and a semiconductor structure are provided. An example field effect transistor includes: a substrate structure, a source, a drain, and a gate. The source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain. A channel layer is formed in the channel region, and N carbon nanotubes extending in the first direction are embedded in the channel layer, where N is an integer greater than or equal to 1. Two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path. The gate is formed on the channel layer. In the channel region between the source and the drain, electron conduction is implemented by using the carbon nanotube disposed in the channel layer.

Field effect transistor and preparation method thereof, and semiconductor structure

A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.

Data processing system and method

Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.

Error correction method and apparatus

A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_that is output by the phase lock loop PLL, and to output a second clock signal clk_. A plurality of child node circuits () are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_based on the second clock signal clk_. The clock grid () and the clock tree () are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

Clock circuit in a processor integrated circuit

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Shenzhen, China

Wen Yin