United Semiconductor (xiamen) Co., Ltd.

Wen Yi Tan

Chin-Chun Huang

Shih-Hsien Huang

Sheng-Hsu Liu

Jinjian Ouyang

Yuan-Chi Pai

Hailong Gu

You-Di Jhang

Guang Yang

Linshan Yuan

Bin Guo

Ji He Huang

Maohua Ren

Xiang Bo Kong

Dejin Kong

Chih-Chien Huang

Yun-Pin Teng

Ching-Shu Lo

Jiawei Lyu

Dian Han Liu

Kuo Liang Huang

Yunfei Fu

Yuheng Liu

Min-Hsien Chen

Jianhua Chen

Kuo-Liang Huang

Jung-Chun Yen

Jun Wu

Xijun Guo

Ming Xuan Ren

Tao Liu

Feng Gao

Han-Min Huang

William Zheng

Xia Yuan

Hui Feng Chen

Shih-Jie Lin

Yong Xie

Chien-Chih Wang

Qun Feng Liu

Kai Ping Huang

Chao Wu

Chung-Li Chien

Cheng-Tar Lu

Zi Xin Chen

Sheng Kai Wang

Xiongwu He

Haipeng Zhu

Weiguo Xu

You Sheng Yin

Hui Min Chen

Xianlei Zhang

Rui Ju

Ching-Ning Yang

Song Gu

Ching-Wen Teng

Fujin Wang

Long Wang

Shi Teng Zhong

Yuchun Guo

Wei-Chun Chang

Shuzhi Zou

Cheng Hua Wu

Sen Mao Feng

Zijun Sun

Qiang Gao

Rong He

Penghui Lu

Zhi Xiang Qiu

Zhen Yu Sui

Bing Xin Xu

Shih-Feng Su

Xin Zhi He

A machine monitoring system includes a plurality of first machines and a control module. The first machines are for a first process. The control module is connected with the first machines. The control module is configured to: define each of the first machines as a high-risk first machine or a low-risk first machine according to a first risk score of each of the first machines; designate one of the first machines being defined as the high-risk first machine as a selected high-risk first machine; assign an object to be processed by the first process through the selected high-risk first machine to obtain a processed object; and determine whether to continue or stop to use the selected high-risk first machine according to a test result of the processed object.

Machine monitoring system and machine monitoring method

A cleaning process of wafer polishing pad, the process includes providing a wafer polishing pad, performing a planarization process with the wafer polishing pad, leaving a residue on the wafer polishing pad after the planarization process, and performing a cleaning step with a cleaning nozzle to remove the residue, the cleaning nozzle comprises at least one Y-shaped pipe, one end of which is a water outlet, and the other two ends are respectively a water inlet and an air inlet, wherein a cleaning liquid flows from the water inlet to the water outlet, and a pressurized gas flows in from the air inlet.

Cleaning process of wafer polishing pad and cleaning nozzle

A semiconductor manufacturing method includes providing a substrate, forming a silicon germanium epitaxial layer in the substrate, forming a first silicon layer on the silicon germanium epitaxial layer, wherein the first silicon layer is a pure silicon layer, and forming a second silicon layer on the first silicon layer, wherein the second silicon layer comprises a silicon layer doped with boron atoms, wherein the boron-doped silicon layer does not comprise germanium.

Method for forming an epitaxial layer with better quality

An overlay mark includes a bottom overlay mark on a bottom level, a middle overlay mark on a middle level, and a top overlay mark on a top level. The bottom overlay mark, the middle overlay mark and the top overlay mark vertically overlap with one another.

Overlay mark

The invention provides a semiconductor manufacturing process, which comprises the following steps: using a computer system to define plurality of shots on a wafer range, distributing a plurality of observation points in each shot, finding out parts of incomplete shots from all of the shots, calculating the number of observation points in each incomplete shot, eliminating the incomplete shots with the number less than 3 observation points, counting all observation points in the remaining incomplete shots, and deleting a part of observation points until the total number of observation points meets a preset total number, and uniformly distributing all observation points, and performing an overlay measurement step on the remaining observation points to generate an offset vector map.

Semiconductor manufacturing process

A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.

Semiconductor device and method for fabricating the same

The invention provides a semiconductor cleaning step, which comprises the following steps: providing a chamber with a bottom surface and a sidewall, the chamber contains a heater on the bottom surface, performing a first deposition step to leave a residual layer on the sidewall of the chamber, performing a carbon deposition step to form a carbon layer on at least the surface of the heater, and performing a plasma cleaning step to simultaneously remove the residual layer on the sidewall of the chamber and the carbon layer on the bottom surface.

Semiconductor cleaning step

A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.

Resistive memory device

A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.

Reticle thermal expansion calibration method capable of improving sub-recipe

A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.

Resistive random access memory and method of forming the same

A lithography film stack applied to an immersion lithography process includes a photoresist, a wavelength adjusting layer and a top coating layer. The photoresist is disposed on a substrate. The wavelength adjusting layer is disposed on the photoresist. The top coating layer is disposed on the wavelength adjusting layer. A refractive index of the wavelength adjusting layer is greater than a refractive index of the top coating layer and a refractive index of an immersion fluid of the immersion lithography process.

Lithography film stack and lithography method

An apparatus for thermally processing a substrate includes a substrate support for holding the substrate and lamps disposed above the substrate support. The lamps are grouped into concentric lamp zones including a center zone comprised of a center lamp and peripheral lamps surrounding the center lamp. A center sleeve is coupled to the center lamp and peripheral sleeves are coupled to the peripheral lamps, respectively, for directing radiated heat to the substrate during thermal processing. The center sleeve has a higher surface roughness than that of the peripheral sleeves.

Apparatus for thermally processing a substrate

A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

Method for forming a semiconductor structure

A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Method for making semiconductor device using a stress memorization technique

A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Semiconductor device having inter-metal dielectric patterns and method for fabricating the same

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Fujian, China

Wen Yi Tan