Taiwan Semiconductor Manufacturing Comp. Ltd.

Anpec Electronics Corporation

Industrial Technology Research Institute

Wen-Yen Chen

Huicheng Chang

Li-Ting Wang

Liang-Yin Chen

Chih-Hao Chen

Su-Hao Liu

Yee-Chia Yeo

Ming-Hung Chang

Ying-Lang Wang

Tai-Yen Peng

Kuo-Ju Chen

Shu-Huei Suen

Tz-Shian Chen

Syun-Ming Jang Jang

Tai-Chun Huang

Bo-Cyuan Lu

Wei-Ting Chien

Jiann-Horng Lin

Wan-Chen Hsieh

Cheng-Li Fan

Ying-Hao Wu

Yi-Chang Lee

Cheng-Jung Sung

Li-Heng Chen

Shih-Hua Tseng

Yi-Wei Chiu

Jyu-Horng Shieh

Ming-Chung Liang

Tsai-Yu Huang

Po-Ju Chen

Jing-Huei Huang

Chin-Hone Lin

Ta-Chuan Liu

Pin-Yung Chen

Yi-Chao Wang

Wei-Han Huang

Fang-Yi Wu

Shin-Hsiang Chien

Kuan-Nan Liu

Kuan Nan Liu

Chuang-Shun Xu

A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Trench filling through reflowing filling material

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.

Methods of forming alignment structure with trenches for semiconductor devices

A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Apparatus, system, and method for measuring the temperature of a substrate

In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Transistor contacts and methods of forming the same

A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

Processes for reducing line-end spacing

Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.

Patterning methods for semiconductor devices and structures resulting therefrom

Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Source/drain structure

A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Melt anneal source and drain regions

In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

Pattern formation method and method for manufacturing a semiconductor device

A circuit measuring device and a method thereof are provided. A voltage source supplies a common voltage such that a calibration current having a preset current value flows from a current-voltage converter to a final test machine. The current-voltage converter converts the calibration current into a calibration voltage. At this time, a voltage sensing component senses a voltage between an input terminal and an output terminal of the current-voltage converter to output sensed calibration data. The current-voltage converter converts a tested current outputted by a tested circuit into a tested voltage. At this time, the voltage sensing component senses the voltage between the input terminal and the output terminal of the current-voltage converter to output actual sensed data. When the final test machine determines that a difference between the sensed calibration data and the actual sensed data is larger than a threshold, the tested circuit is adjusted.

Circuit measuring device and method

A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Melting laser anneal of epitaxy regions

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Hsinchu, Taiwan

Wen-Yen Chen