Altera Corporation

Wen Wu

Yanzhong Xu

Jeffrey T Watt

Nelson Joseph Gaspard

Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset signal. The multiplexer may also receive a normal clock signal and a delayed clock pulse signal that is triggered in response to detecting assertion of the reset signal.

Register circuitry with asynchronous system reset

Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by forming the fin or fins and then forming the trapping region at the base of the fin. Illustratively, the trapping region is formed by implanting in the substrate ions having a conductivity type opposite that of the substrate or by creating defects in the substrate or by epitaxially growing a region or regions having an opposite conductivity type to that of the substrate.

FinFET with improved SEU performance

Integrated circuits with clocked storage elements are provided. A clocked storage element such as a flip-flop circuit may include a master latch, a slave latch, and associated control circuitry. The master and slave latches may be implemented using dual-interlocked cell (DICE) latch configurations. The DICE latch may include at least four inverting circuits having two redundant node pairs and may exhibit immunity to soft error upset (SEU) events. Each of the master and slave latches may be separated into different portions so that the redundant nodes are physically separated by interposing circuitry. The redundant nodes may also be formed in separate wells to further minimize charge sharing. The different portions of the master and slave latch may be interleaved to minimize area.

Growing community of inventors

Mountain View, CA, United States of America

Wen Wu