Mosel Vitelic Corporation

Wen-Wei Lo

Chung-Cheng Wu

Li-Chun Li

Huoy-Jong Wu

Saysamone Pittikoun

Tzung-Rue Hsieh

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

Method for fabricating an integrated circuit with a transistor electrode

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material. The planarizing method of the invention has the advantage of not requiring a photolithography step required in a prior art planarization process. In addition, the planarization method of the invention has the advantage of not requiring a process step that subjects an integrated circuit to relatively high temperatures that can have adverse effects on metal conductors present therein.

Global planarization method for inter-layer-dielectric and inter-metal dielectric

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

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Panchiao, Taiwan

Wen-Wei Lo