Realtek Semiconductor Inc.

Kaohsiung Medical University

Wen-Wei Lin

Ching-Sheng Cheng

Kuan-Chia Huang

Tian-Lu Cheng

Steve R Roffler

I-Ju Chen

A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Memory device of reducing the number of calibration resistors and control method thereof

The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

Control method of multiple memory devices and associated memory system

A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

Method for simultaneously accessing first DRAM device and second DRAM device and associated memory controller

A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.

Method of memory time division control and related device

The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.

Memory circuit and method thereof

The present invention is related to a method for detecting a protein comprising: (1) providing a fusion protein, wherein the fusion protein comprises the protein which is fused with a secondary antibody detected protein tag, wherein the secondary antibody detected protein tag comprises at least one epitope selected from the Fc region of at least one primary antibody which is capable of being detected by a corresponding secondary antibody; (2) contacting the fusion protein with a secondary antibody which binds to the secondary antibody detected protein tag to form a protein/antibody complex; and (3) detecting the protein/antibody complex.

Method for detecting protein by using secondary antibody detected epitope tag

A method of preparing an epitope for a secondary antibody detected protein tag, comprising: constructing a expressing vector, comprising a nucleotide sequence for encoding the secondary antibody detected protein tag comprising at least one epitope selected from at least one primary antibody which is detected by corresponding secondary antibody; expressing the vector in a host cell; and obtaining the secondary antibody detected protein tag which is expressed in the host cell. Further, a method for constructing a protein molecular weight marker ladder, comprising constructing a plurality of recombinant protein tags with different molecular weights, wherein each the recombinant protein tag comprises at least one epitope of primary antibody. Besides, a secondary antibody detected protein tag comprises at least two peptide sequences of epitopes selected from primary antibodies of at least two different species.

Growing community of inventors

Hsinchu, Taiwan

Wen-Wei Lin