International Business Machines Corporation

Wen-Tzer Thomas Chen, Jr

William A Maron

Diane Garza Flemming

Mysore Sathyanaranyana Srinivas

Robert H Bell, Jr

Danny Marvin Neal

Richard Allen Kelley

Frank Eliot Levine

Steven Mark Thurber

Jimmie Earl DeWitt, Jr

David Blair Whitworth

Enio Manuel Pineda

Bruce Gerard Mealey

Vaijayanthimala K Anand

Venkat Rajeev Indukuru

Basu Vaidyanathan

Renato John Recio

Ram Raghavan

Madhavi Gopal Valluri

Pattabi Michael Seshadri

Charles Ray Johns

Andrew Henry Wottreng

Mysore Sathyanarayana Srinivas

Shih-Gong Li

Hong Lam Hua

Gary Yuh Tsao

David Arlen Elko

Richard Louis Arndt

Richard James Eickemeyer

Bradly George Frey

Ian David Judd

Alexander Erik Mericas

Bruce Leroy Beukema

Peichun Peter Liu

Patrick Allen Buckland

John-David Wellman

Calvin Lui Sze

Sandy K Kao

Donald Ray Stence

Yat Hung Ng

Kevin C Stelzer

Pattabi R Seshadri

Earl James McDonald

According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes assigning to a first set of virtual resources associated with a virtual machine a first priority and assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority. An operating system of the virtual machine is provided with the first and second priorities assigned to the respective first and second sets of virtual resources. The operating system dispatches to process a workload the virtual resources from the first set before dispatching the virtual resources from the second set.

Hybrid virtual machine configuration management

A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.

Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.

Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code

A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.

Performance of processors is improved by limiting number of branch prediction levels

A mechanism is provided for sharing resources allocated to an entitled virtual machine (VM). A blocked domain is created around the entitled VM and one or more processors allocated to the entitled VM. A first dispatching algorithm is implemented that prevents the dispatching of processes from other operating systems within other VMs to the one or more processors allocated to the entitled VM. Responsive to utilization of the one or more processors allocated to the entitled VM falling below a predetermined threshold, a second dispatching algorithm is implemented that allows dispatching of processes from the other operating systems within the other VMs to the one or more processors allocated to the entitled VM.

Sharing resources allocated to an entitled virtual machine

A method for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Using a plurality of tables for improving performance in predicting branches in processor instructions

A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources.

A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Performance in predicting branches

According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.

Variable cache line size management

According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

Growing community of inventors

Austin, TX, United States of America

Wen-Tzer Thomas Chen, Jr