Taiwan Semiconductor Manufacturing Comp. Ltd.

National Science Council

Wen-Tung Chen

Horng-Huei Tseng

Che-Cheng Chang

Yu-Cheng Liu

Hung-Hao Chen

Hsiang-Ku Shen

Chih-Hung Lu

Chin-Ping Yang

Han-Yi Chen

Hsiang-Yu Tsai

Jian-Ming Huang

Ecko Lu

A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Removing polymer through treatment

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Semiconductor device and method of manufacture

Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Process for forming metal-insulator-metal structures

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

MIM capacitor with top electrode having footing profile and method forming same

Etching process control in forming MIM capacitor

A compound or polymer having a bis(phenoxy)naphthalene structure, a high molecular weight, and very good mechanical performance and heat-resistivity is provided. The polymer can be polyamides, polyimides or poly(amide-imide)s and can have a basic structure of ##STR1## wherein R1 is a naphthalene ring.

Bis(4-aminophenoxy)naphthalene and its polymers

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Taipei, Taiwan

Wen-Tung Chen