Macronix International Co., Ltd.

Wen-Tsung Huang

Shih-Yu Wang

Chih-Wei Hsu

Ming-Yin Lee

An electrostatic discharge circuit includes a discharge switch, a first trigger circuit and a second trigger circuit. A first terminal of the discharge switch is coupled to a first power domain, and a second terminal of the discharge switch is coupled to a second power domain. The first trigger circuit is coupled between the first terminal and a control terminal of the discharge switch. The second trigger circuit is coupled between the second terminal and the control terminal. When an electrostatic discharge voltage occurs in the first power domain, the second trigger circuit is configured to form a conduction voltage between the second terminal and the control terminal to turn on the discharge switch. When the electrostatic discharge voltage occurs in the second power domain, the second trigger circuit is configured to short the second terminal and the control terminal to turn on the discharge switch.

Electrostatic discharge circuit

The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.

Electrostatic discharge protection apparatus and its operating method

A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.

Thyristor

An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.

Input output circuit and electrostatic discharge protection circuit

The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

Semiconductor device and electrostatic discharge protection method

An ESD protection apparatus includes first and second parasitic bipolar junction transistors having different majority carriers formed in a substrate and an ESD protection device having a grounding end and a connecting end connected to the first parasitic bipolar junction transistor. When an ESD voltage applied to the ESD protection apparatus is greater than a ground voltage, a first current is grounded by passing through one of a first assembled protecting circuit including the first parasitic bipolar junction transistor and the ESD protection device and a second assembled protecting circuit including the first and the second parasitic bipolar junction transistor; and when an ESD voltage applied to the ESD protection apparatus is less than a ground voltage, a second current coming from a ground is directed to a voltage source by passing through the other one of the first assembled protecting circuit and the second assembled protecting circuit.

Electrostatic discharge protection apparatus and applications thereof

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.

A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.

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Changhua County, Taiwan

Wen-Tsung Huang