Himax Technologies, Inc.

Wen-Teng Fan

Chien-Ru Chen

Shih-Chun Lin

Ying-Lieh Chen

Chuan-Che Lee

Yu-Jui Chang

Kai-Lan Chuang

Yu-Jen Yen

Chan-Fei Lin

Chao-Ching Chi

A method for transmitting image data in a display is provided. The method includes the steps of: sending first pixel data through a first bus to a source driver; sending second pixel data through a second bus to the source driver; reorganizing the first pixel data and the second pixel data in the source driver; and generating third pixel data according to the reorganization of the first pixel data and the second pixel data for channels in the source driver. A display is also disclosed herein.

Method for transmitting image data through RSDS transmission interfaces

A display and a method for signal transmission of the display are provided. The display has a source driver, a panel, and a timing controller having at least one data pin and a clock signal pin. The timing controller sends a clock signal to the source driver via the clock signal pin, and then sends a start pulse pattern to the source driver via the at least one data pin such that the source driver is notified to receive setting signals and display data signals. The source driver drives the panel according to the setting signals and the display data signals received from the timing controller via the at least one data pin. One or more of the setting signals are received by the source driver within every clock of the clock signal.

Display and method thereof for signal transmission

The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Timing controller and clock signal detection circuit thereof

A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

Phase selector

Provided is a decoder for receiving a digital data and outputting an analog voltage. The decoder comprising a main switch array, a first pre-decoding switch array, and a second pre-decoding switch array. The main switch array receives the digital data and outputs a voltage if the digital data is in a first range. The first pre-decoding switch array is for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range. The second pre-decoding switch array is for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range. Combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is in a substantially rectangular layout structure.

Compact layout structure for decoder with pre-decoding and source driving circuit using the same

A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).

Spread-spectrum generator

The present invention provides a liquid crystal display comprising a display panel, a plurality of gate drivers sequentially enabling rows of pixels of the display panel, a plurality of source drivers outputting a plurality of driving signals to the enabled row of the pixels of the display panel, and a timing controller outputting each of a plurality of start pulses to all the source drivers and sequentially enabling the source drivers so that each source driver respectively receives one of the start pulses, wherein each of the source drivers latch a plurality of image signals when receiving one of the start pulses.

Liquid crystal display driving circuit and method thereof

In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced.

Driving circuits in electronic device

A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.

Level shift circuit and method thereof

A source driver of an LCD includes a first and second power sources, a first and second inversion units, a first and second charging switches, and a first and second discharging switches. The first charging switch is coupled to the first power source, a first end of the first inversion unit, and a second end of the second inversion unit. The second charging switch is coupled to the first power source, a first end of the second inversion unit, and a second end of the first inversion unit. The first discharging switch is coupled to the second power source, the second end of the first inversion unit, and the first end of the second inversion unit. The second discharging switch is coupled to the second power source, the second end of the second inversion unit, and the first end of the first inversion unit.

Integrated circuit capable of synchronizing multiple outputs of buffers

The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying a pumped voltage based on a voltage source and a buffer powered by the pumped voltage and outputting a buffered data signal based on the data signal.

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Tainan County, Taiwan

Wen-Teng Fan