United Microelectronics Corp.

Carux Technology Pte. Ltd.

Wen-Tai Chiang

Chien-Ting Lin

Shih-Hung Tsai

Ssu-I Fu

Ying-Tsung Chen

Chun-Hsien Lin

Chih-Wei Chen

Cheng-Tzung Tsai

Chen-Hua Tsai

Yu-Cheng Tung

Chin-Fu Lin

Chi-Mao Hsu

Chih-Wei Yang

An-Chi Liu

Wei-Tsun Shiau

Po-Wei Liu

Yi-Sheng Hsieh

Wei-Min Lin

Chin-Cheng Chien

Chien-Liang Lin

Chiu-Hsien Yeh

Shao-Wei Wang

Ted Ming-Lang Guo

Yi-Cheng Chang

Kai-Ping Wang

An electronic device includes a plurality of light-emitting elements, a temperature sensor, and a control element. The control element includes a storage unit, a comparison unit, and a first control unit. The storage unit stores a look-up table including different correspondences between different temperature ranges and different power thresholds. The comparison unit receives the first power consumption of the light-emitting elements, determines the predetermined power threshold in the different correspondences of the look-up table according to the ambient temperature, and compares the first power consumption with the predetermined power threshold to determine the second power consumption. The first power consumption is obtained by measuring the light-emitting elements. The first control unit drives the light-emitting elements according to the second power consumption.

Electronic device and control method thereof

A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Manufacturing method of metal oxide semiconductor transistor

A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Fin-shaped field-effect transistor process

The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Metal oxide semiconductor transistor and manufacturing method thereof

FinFET and fabricating method thereof

A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Semiconductor device having metal gate and manufacturing method thereof

A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Semiconductor structure

A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Manufacturing method for semiconductor device having metal gate

A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Method of forming semiconductor device having metal gate

A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

Semiconductor process

The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor.

Method of forming semiconductor device

A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Semiconductor structure and method of fabricating the same

A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Growing community of inventors

Tainan, Taiwan

Wen-Tai Chiang