Siliconware Precision Industries Co., Ltd.

Siliconware Precision Industries, Ltd.

Wen-Ta Tsai

Lian-Cherng Chiang

Chieh-Ping Huang

Chien-Ping Huang

Chin-Te Chen

Yuan-Fu Lin

Yuan-Ping Joe

Shi-Yu Chang

Chin Fa Wang

A semiconductor package and a fabrication method thereof are provided, in which a ground pad on a chip is electrically connected to a ground plane on a substrate by means of an electrically-conductive wall formed over a side surface of the chip and an electrically-conductive adhesive used for attaching the chip to the substrate. Therefore, a wire-bonding process is merely implemented for power pads and signal I/O (input/output) pads on the chip without having to form ground wires on the ground pads for electrical connection purposes. This benefit allows the use of a reduced number of bonding wires and simplifies wire arrangement or routability. And, a grounding path from the chip through the electrically-conductive wall and electrically-conductive adhesive to the substrate is shorter than the conventional one of using ground wires, thereby reducing a ground-bouncing effect and improving electrical performances of the semiconductor package.

Semiconductor package with enhanced chip groundability and method of fabricating the same

A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe. Since the support members can provide good support to the bonding pads on the second integrated circuit chip, it can help prevent the chips from being cracked during the manufacture process. The manufactured dual-chip integrated circuit package can be thus reliable in quality.

Dual-chip integrated circuit package and method of manufacturing the same

A delamination-preventing substrate and a semiconductor package with the substrate are provided. A metal layer and a solder mask layer are sequentially laminated on a chip attach area of a substrate, and both formed with corresponding openings for partly exposing the substrate. This allows an adhesive for chip-bonding use to be directly attached to the substrate via the openings, so as to reduce contact area between the adhesive and the metal layer, and to increase bonding between the substrate and a chip mounted on the substrate by means of the adhesive. Direct contact between the adhesive and the substrate also helps reduce stress generated between the chip and substrate, thereby preventing stress-induced delamination. Due to weak adhesion between adhesive and metal materials, reduced contact area between the adhesive and the metal layer would further enhance bonding of the chip to the substrate, thereby assuring quality of fabricated package products.

Delamination-preventing substrate and semiconductor package with the same

Chair

Chair armrest

A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires. The use of the extending portion for the attachment of the two integrated circuit chips can help prevent delamination of the chips and can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process. The manufactured integrated circuit package can therefore be more assured in reliability and quality.

Dual-chip integrated circuit package with a chip-die pad formed from leadframe leads

A wafer sawing/grinding process capable of removing cracks and chipping resulted from a wafer sawing operation. A silicon wafer having an active surface and a back surface is provided. A first tape is attached to the back surface of the wafer and then the wafer is sawn along kerfs between neighboring silicon chips. A second tape is attached to the active surface of the silicon wafer before removing the first tape. The back surface of the wafer is then ground until the wafer reaches a desired thickness. A third tape is attached to the ground back surface of the wafer before removing the second tape.

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Taichung, Taiwan

Wen-Ta Tsai