Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Shuo Hsieh

Chih-Han Lin

Shih-Chang Tsai

Te-Yung Liu

Ryan Chia-Jen Chen

Shu-Yuan Ku

Ya-Yi Tsai

Ming-Jie Huang

Chieh-Ning Feng

A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.

Semiconductor devices with interface between gate isolation structure and dummy channel having curved profile and methods of manufacturing thereof

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

Semiconductor device and manufacturing method thereof

Semiconductor devices with gate isolation structures and methods of manufacturing thereof

A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.

Gate isolation plugs structure and method

A method for fabricating a semiconductor device is provided including an opening in a gate electrode layer to form two spaced apart gate electrode layers. An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers. A first insulating layer is formed in the opening between the two spaced apart gate electrode layers.

A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.

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Taipei, Taiwan

Wen-Shuo Hsieh