Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Vanguard International Semiconductor Corporation

University of California

Wen-Shiang Liao

Chewn-Pu Jou

Feng-Wei Kuo

Huan-Neng Chen

Feng Wei Kuo

Chih-Hang Tung

Chen-Hua Douglas Yu

Lan-Chou Cho

Wei-Tsun Shiau

William Wu Shen

Ying-Chih Hsu

Min-Hsiang Hsu

Hung-Lin Shih

Tsan-Chi Chu

Jianglin Du

Chuei-Tang Wang

Robert Bogdan Staszewski

Erik S Jeng

Chieh-Yen Chen

Jiunn-Ren Hwang

Wen-Ching Tsai

Kuan-Yang Liao

Chun-Yao Chen

Chao-Ming Koh

Ching-Hui Chen

Tzu-Shih Yen

Yanghyo Kim

Hsiao-Chin Tuan

Wan-Yih Lien

Ching-Ying Lee

Eddy Chiang

Chun-Ju Huang

A method of forming a semiconductor structure includes: providing a first inter-level dielectric (ILD) layer overlying a molding layer, the molding layer including a transmitter ground structure and a receiver ground structure; forming first openings through the first ILD layer to expose the transmitter and receiver ground structures; forming first lower transmitter and receiver electrodes in the first openings to be respectively coupled to the transmitter and receiver ground structures; forming a first dielectric waveguide overlying the first ILD layer, and first lower transmitter and receiver electrodes; depositing a second ILD layer overlying the first dielectric waveguide; forming second lower transmitter and receiver electrodes extending through the second ILD and respectively coupled to the transmitter and receiver ground structures; and forming a second dielectric waveguide overlying the second ILD layer and the second lower transmitter and receiver electrodes.

Semiconductor structure having multiple dielectric waveguide channels and method for forming semiconductor structure

A package structure includes a first redistribution structure, an insulating material over the first redistribution structure, a die embedded in the insulating material, a second redistribution structure over the die and the insulating material, and a first via extending through the insulating material, wherein the first via includes a first inner conductive core, and a first outer conductive shielding layer, wherein the insulating material is disposed between the first inner conductive core and the first outer conductive shielding layer, and wherein the first outer conductive shielding layer has an annular shape in a top-down view.

Low-noise package and method

This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die. Each of the one or more antenna structures can be positioned over the one or more antenna regions.

Antenna package for signal transmission

A semiconductor structure includes an antenna pad, a ground plane and a plurality of conductive vias. The ground plane is disposed over the antenna pad and includes a plurality of first conductive patterns separated from one another. The conductive vias are disposed between the antenna pad and the ground plane. The plurality of conductive vias are arranged to surround an area of the antenna pad and electrically connected to the antenna pad, and the plurality of first conductive patterns are overlapped with the area of the antenna pad.

Semiconductor structures and method of forming the same

A package having a capacitor structure and a method of forming the same are provided. The package includes a first die; a second die bonded onto the first die; an isolation region disposed on the first die and laterally encapsulating the second die; at least one first through-via disposed aside the second die and penetrating through the isolation region; an electrode layer disposed on the at least one first through-via; and a capacitor dielectric layer disposed between the at least one first through-via and the electrode layer to separate the at least one first through-via from the electrode layer, wherein the at least one first through-via, the capacitor dielectric layer, and the electrode layer constitute a capacitor structure.

Package having embedded decoupling capacitor and method of forming the same

A package structure includes a first die, an insulating material around the first die, a first antenna extending through the insulating material, wherein the first antenna includes a first conductive plate extending through the insulating material and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is disposed between the plurality of first conductive pillars and the first die, and a first high-k block embedded in the insulating material, wherein the first high-k block is disposed between the first conductive plate and the plurality of first conductive pillars, and wherein the first high-k block comprises a material having a dielectric constant that is different than a dielectric constant of the insulating material.

Antenna apparatus and method

A thermally tunable waveguide including an optical waveguide and a heater is provided. The optical waveguide includes a phase shifter. The heater is disposed over the optical waveguide. The heater includes a heating portion, pad portions and tapered portions. The heating portion overlaps with the phase shifter of the optical waveguide. The pad portions are disposed aside of the heating portion. Each of the pad portions is connected to the heating portion through one of the tapered portions respectively.

Thermally tunable waveguide and photonic integrated circuit component having the same

A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

Apparatus and method for generating a parameterized waveguide optical elements

Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Integrated fan-out package with 3D magnetic core inductor

A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias, second conductive vias, and a third conductive via between the first conductive vias and the second conductive vias. The connecting metal line is between, and non-overlapped with, the first conductive via and the second conductive vias vertically from a cross-sectional view.

Semiconductor package device with integrated inductor and manufacturing method thereof

A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.

Semiconductor package with antenna and method of forming the same

A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Embedded metal insulator metal structure

A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.

Interposer directly bonded to bonding pads on a plurality of dies

A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Growing community of inventors

Miaoli County, Taiwan

Wen-Shiang Liao