Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Shen Chou

Yung-Chow Peng

Yu-Tao Yang

Po-Zeng Kang

Yung-Hsu Chuang

Chih-Chiang Chang

Chin-Hua Wen

Jie-Ren Huang

Jaw-Juinn Horng

Yun-Ru Chen

Jui-Feng Kuan

Hui Yu Lee

Chi-Wen Chang

Mei-Chen Chuang

Bindu Madhavi Kasina

Brady Yang

Yi-Kan Cheng

Chih-Hsien Chang

Jui-Cheng Huang

Ying-Chih Hsu

Ching-Ho Chang

Yu-Jen Lai

Chi-Ping Yao

Alan S Roth

Eric Soenen

Chia-Chung Chen

Chung-Chieh Yang

Chung-Peng Hsieh

Justin Shi

Szu-Chun Tsao

Wan-Te Chen

Ya Yun Liu

You-Cheng Xiao

Guang-Cheng Wang

Chih-chiang Chang

Shenggao Li

Robit Yang

Ying-Chi Hsu

Ming-Cheng Syu

Shu-Chin Tai

A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated in response to the core voltage either at the disabling voltage level or at the enabling voltage level.

Power on control circuits and methods of operating the same

In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.

Stack-gate circuit

A semiconductor device includes a plurality of active area structures extending in parallel, first and second dummy gate layers spanning the plurality of active area structures, a first active device including first portions of the plurality of active area structures between the first and second dummy gate layers, a metal layer spanning the plurality of active area structures between the first and second dummy gate layers, and a pair of vias positioned at opposite ends of the metal layer. A first via of the pair of vias is configured to be electrically connected to ground, and a second via of the pair of vias is configured to be electrically connected to a current source and a circuit configured to measure a voltage at the node.

Temperature monitoring device and method

Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints. In embodiments, the plurality of maximum voltage change values are stored in the form of a matrix in an extensible markup language (XML) file.

Systems and methods for providing a dynamic high voltage circuit design workflow

A semiconductor device includes a plurality of transistors, a plurality of metal layers, and a resistor. The plurality of transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The plurality of metal layers are overlaid above the plurality of transistors. The resistor is implemented between two of the plurality of metal layers.

Semiconductor device with source resistor

A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

High voltage guard ring semiconductor device and method of forming same

An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

Integrated circuit device, method, layout, and system

A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Automatic generation of layouts for analog integrated circuits

Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Pre-characterization mixed-signal design, placement, and routing using machine learning

Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Automatic generation of sub-cells for an analog integrated circuit

A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Transition cells for advanced technology processes

A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

System for designing a semiconductor device, device made, and method of using the system

A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.

Growing community of inventors

Zhubei, Taiwan

Wen-Shen Chou