Micron Technology Incorporated

Other

Round Rock Research, LLC

Merck + Co., Inc.

Wen Qian Li

Christopher K Morzano

Mark R Thomann

Manny K Ma

Aaron M Schoenfeld

William F Jones

R Jacob Baker

Daniel R Loughmiller

Scott E Schaefer

Timothy B Cowles

Kevin J Ryan

Gary M Johnson

Jeff W Janzen

Raphael Wong

Rajesh Somasekharan

Konstantin Petrukhin

Kang Zhang

Kerkong Tung

Michael D Chaine

Sugato Mukherjee

A drug test device for bodily fluids, such as urine, includes a cup and a removable lid which houses one or more test strips. The lid is releasably locked onto the cup so as to align dipping ends of the test strips exposed through an underside of the lid with a position stabilizer, thereby causing the dipping ends to be located downwardly and submerged in fluid when the device is placed on its side in a reactive position. The position stabilizer may comprise a sidewall indentation that reduces the internal volume of the cup and keeps the cup from rolling when placed on its side.

Fluid specimen collection device

An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Method and apparatus for providing symmetrical output data for a double data rate DRAM

A method and apparatus are provided for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus are disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a system clock signal by delaying the system clock signal. A falling edge of the local timing signal is established and phase-locked to a falling edge of the system clock signal by further delaying only a portion of a signal representative of the delayed clock signal. By separately delaying different portions of the system clock signal and using the separately delayed portions to establish a local timing signal, a local timing signal may be established which is compensated for the varied effects of delay elements in a delay locked loop.

Method and apparatus for output data synchronization with system clock in DDR

A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Parallel-to-serial data sort device

A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

Data strobe synchronization circuit and method for double data rate, multi-bit writes

A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Method and apparatus for converting parallel data to serial data in high speed applications

A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Phase detector and method having hysteresis characteristics

A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., '1100,' is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

DDR II write data capture calibration

An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O) buffer can be enabled and disabled in response to an ODT control signal. Additionally, the ODTs for a first set of the buffer circuits can be enabled and disabled responsive to the ODT control signal and the ODT for at least one of a second set of the buffer circuits is disabled.

Apparatus and method for independent control of on-die termination for output buffers of a memory device

Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Growing community of inventors

Hacienda Heights, CA, United States of America

Wen Qian Li