Globalfoundries Inc.

Wen-Pin Peng

Min-Hwa Chi

Yong Meng Lee

Yue Hu

Huang Liu

Xin Wang

Garo Jacques Derderian

Xusheng Kevin Wu

Sipeng Gu

Suraj Kumar Patil

Zhiguo Sun

Changyong Xiao

Sandeep Gaan

Lun Zhao

Wei Hua Tong

Jean-Baptiste Laloe

Danni Chen

Meng Luo

Jialin Weng

Wei-Hua Tong

Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

Method for forming a metal gate including de-oxidation of an oxidized surface of the metal gate utilizing a reducing agent

Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

Stress memorization and defect suppression techniques for NMOS transistor devices

In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

Forming self-aligned NiSi placement with improved performance and yield

A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0&#xb0; angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.

MOL contact metallization scheme for improved yield and device reliability

Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.

Spacer to prevent source-drain contact encroachment

Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Semiconductor structures with bridging films and methods of fabrication

Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

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Clifton Park, NY, United States of America

Wen-Pin Peng