Nan Ya Technology Corporation

Wen-Ming Lee

Chuan-Jen Chang

A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Control circuit and control method for controlling delay lock loop in dynamic random access memory

A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.

Memory apparatus and voltage control method thereof

A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.

Memory apparatus and operating method thereof

The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. the computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.

Frequency-adjusting circuit, electronic memory, and method for determining a refresh frequency for a plurality of dram chips

The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Detecting circuit, DRAM, and method for determining a refresh frequency for a delay-locked loop module

An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

Clock signal generating circuit and operating method thereof

The present invention provides a dynamic random access memory apparatus includes a first chip and a second chip. The first chip includes a plurality of memory cells and a plurality of through-silicon vias (TSVs). The plurality of memory cells are arranged in an array. First terminals of the TSVs are respectively coupled to the memory cells. The first chip and the second chip are overlapped, the second chip includes a plurality storage capacitors. Second terminals of the TSVs are respectively coupled to the storage capacitors storage capacitors.

Dynamic random access memory apparatus

A temperature sensing system, which comprises: a temperature analyzing circuit, for sensing temperature and generating an analyzing result in response to the sensed temperature; and a control unit, for controlling a temperature sensing time interval; wherein the control unit continuously changes the temperature sensing time interval according to a predetermined temperature range in response to the sensed temperature.

Growing community of inventors

Miaoli County, Taiwan

Wen-Ming Lee