University of Illinois

International Business Machines Corporation

Other

University of Virginia

Impact Technologies, LLC

Wen-mei William Hwu

Jinjun Xiong

Matthew Carl Merten

Lingfei Wu

Zaid Qureshi

Suma Bhat

Hongyu Gong

Jian Huang

Kevin Skadron

I-Hsin Chung

Nam Sung Kim

Mohamed E Aly

Ahmed Abulila

Daniel A Connors

David I August

Vikram Sharma Mailthody

John W Sias

Andrew Raymond Trick

John Christopher Gyllenhaal

Christopher Neith George

A computer-implemented method for generating an abstract meaning representation ('AMR') of a sentence, comprising receiving, by a computing device, an input sentence and parsing the input sentence into one or more syntactic and/or semantic graphs. An input graph including a node set and an edge set is formed from the one or more syntactic and/or semantic graphs. Node representations are generated by natural language processing. The input graph is provided to a first neural network to provide an output graph having learned node representations aligned with the node representations in the input graph. The method further includes predicting via a second neural network, node label and predicting, via a third neural network, edge labels in the output graph. The AMR is generated based on the predicted node labels and predicted edge labels. A system and a non-transitory computer readable storage medium are also disclosed.

Abstract meaning representation parsing with graph translation

A computer-implemented method is provided for transferring a target text style using Reinforcement Learning (RL). The method includes pre-determining, by a Long Short-Term Memory (LSTM) Neural Network (NN), the target text style of a target-style natural language sentence. The method further includes transforming, by a hardware processor using the LSTM NN, a source-style natural language sentence into the target-style natural language sentence that maintains the target text style of the target-style natural language sentence. The method also includes calculating an accuracy rating of a transformation of the source-style natural language sentence into the target-style natural language sentence based upon rewards relating to at least the target text style of the source-style natural language sentence.

Text style transfer using reinforcement learning

The present disclosure relates to systems and methods that provide a reconfigurable cryptographic coprocessor. An example system includes an instruction memory configured to provide ARX instructions and mode control instructions. The system also includes an adjustable-width arithmetic logic unit, an adjustable-width rotator, and a coefficient memory. A bit width of the adjustable-width arithmetic logic unit and a bit width of the adjustable-width rotator are adjusted according to the mode control instructions. The coefficient memory is configured to provide variable-width words to the arithmetic logic unit and the rotator. The arithmetic logic unit and the rotator are configured to carry out the ARX instructions on the provided variable-width words. The systems and methods described herein could accelerate various applications, such as deep learning, by assigning one or more of the disclosed reconfigurable coprocessors to work as a central computation unit in a neural network.

Reconfigurable crypto-processor

Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer ('PLB') in a host bridge associated with the primary memory medium and the secondary memory medium.

FlatFlash system for byte granularity accessibility of memory in a unified memory-storage hierarchy

Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface ('API'), direct access to non-volatile storage independent of a host central processing unit ('CPU') on a control path or data path to perform a read operation and write operation of data.

Providing direct data access between accelerators and storage in a computing environment, wherein the direct data access is independent of host CPU and the host CPU transfers object map identifying object of the data

A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prologue and epilogue are implicitly created and maintained within the hardware in the invention, a significant reduction in code size can be achieved compared to software-only modulo scheduling. Furthermore, loops with iteration counts less than the number of concurrent iterations present in the kernel are also automatically handled. This hardware enhanced scheme achieves the same performance as the fully-specified standard method. Furthermore, the hardware reduces the power requirement as the entire fetch unit can be deactivated for a portion of the loop's execution. The basic design of the invention involves including a plurality of buffers for storing loop instructions, each of which is associated with an instruction decoder and its respective functional unit, in the dispatch stage of a processor. Control logic is used to receive loop setup parameters and to control the selective issue of instructions from the buffers to the functional units.

Method and apparatus for modulo scheduled loop execution in a processor architecture

Disclosed is a method and apparatus for detecting and monitoring program hot spots during execution that may be implemented in hardware. A hot spot detector tracks branch instructions which are retired. Frequently executed branch instruction addresses within a particular interval are designated as hot spot candidates. A hot spot detection counter is used to track non-hot spot branches and hot spot candidate branches. When hot spot candidate branches are frequently encountered compared to non-hot spot candidate branches, the hot spot detector may notify the operating system and hot spot candidate branch addresses may be supplied to a runtime optimizing compiler and a monitor table or a hot spot monitor. The hot spot monitor may disable the hot spot detector when a program is operating in known hot spots and may enable the hot spot detector if the program has strayed from known hot spots.

Method and apparatus for instruction execution hot spot detection and monitoring in a data processing unit

Disclosed is a method and system for handling inline recovery from speculatively executed instructions. Each register may be provided with an E-tag, that, when set, indicates an exception occurred in the generation of the value stored in its register, and an R-tag, which is used to manage data flow dependencies in recovery mode. Recovery is performed by re-executing speculatively those set of speculative instructions that are data flow dependent upon a first excepting speculative instruction. The disclosed invention provides an architecture and method for efficient exception handling when combining control speculation, data speculation and predication, thereby resulting in substantially enhanced instruction level parallelism.

Method and apparatus for enhancing instruction level parallelism

Growing community of inventors

Champaign, IL, United States of America

Wen-mei William Hwu