Chi Mei Optoelectronics Corporation

Pervasive Display Co., Ltd.

Gigno Technology Co., Ltd.

Wen-Jyh Sah

Chin-Cheng Chien

Biing-Seng Wu

Hsin-Hung Chen

Chung-Kuang Wei

Chao-Wen Wu

Chin-Lung Ting

Cheng-Jen Chu

Jenn-Fang Yang

A non-volatile display module has a display panel and a driving circuit. The display panel has a substrate at which at least one scan line, at least one data line and at least one thin film transistor (TFT) are disposed. The TFT is located at an intersection area of the scan line and data line. The driving circuit has a driving unit, a power converting unit and a multiplexing unit. The driving unit receives at least one image controlling signal according to a clock signal. The power converting unit generates a plurality of power signals. The multiplexing unit is electrically connected with the scan line, the data line, the driving unit and the power converting unit, and outputs one of the power signals to the scan line or the data line according to the image controlling signal. A non-volatile display apparatus is also disclosed.

Non-volatile display module and non-volatile display apparatus

A pixel array module includes a substrate, a pixel electrode array, a patterned conductive layer and a semiconductor circuit unit. The substrate has a first surface and a second surface opposite to the first surface. The pixel electrode array is disposed on the first surface of the substrate. The patterned conductive layer is disposed on the second surface of the substrate, and the patterned conductive layer is electrically connected to the pixel electrode array. The semiconductor circuit unit has at least one input terminal and at least one output terminal, which is electrically connected to the patterned conductive layer. A flat display apparatus is also disclosed.

Pixel array module and flat display apparatus

A display module includes a scan line, a data line, a driving circuit and a level converting circuit. The driving circuit has at least one first driving unit and at least one second driving unit electrically connected to the first driving unit. A non-DC signal is transmitted between the first driving unit and the second driving unit for controlling the first driving unit and/or the second driving unit. The first driving unit outputs a first driving signal to the scan line. The second driving unit outputs a second driving signal to the level converting circuit. The level converting circuit is electrically connected with the driving circuit and the data line, and outputs a display signal to the data line according to the second driving signal. A driving method of the display module is also disclosed.

Display module and driving method thereof

A semiconductor chip module includes a first flip-chip unit and a second flip-chip unit. The first flip-chip unit has a first chip and a first glass circuit board. The first chip is connected with the first glass circuit board by flip-chip bonding. The second flip-chip unit has a second chip and a second glass circuit board. The second chip is connected with the second glass circuit board by flip-chip bonding. The first flip-chip unit and the second flip-chip unit are attached to each other. A method for manufacturing the semiconductor chip module is also disclosed.

Semiconductor chip module with stacked flip-chip unit

A method of reducing flickering and inhomogeneous brightness in an LCD. The method serially connects each scan line connecting a plurality of pixels in a row with a resistor to form a scan line circuit. The resistor is connected between the first pixel of the scan line and the voltage input terminal of the scan line, so that the gate voltage entering the TFT in the first pixel deforms. The voltage of the TFT decreases when it is turned off, minimizing screen flickering and inhomogeneous brightness due to the capacitor charge coupling effect between the first pixel and the last pixel on a scan line.

Method of reducing flickering and inhomogeneous brightness in LCD

The invention provides a manufacturing process of transflective TFT-LCD panel (transflective TFT-LCD panel) comprising the following steps: first, form a first conductive layer on the substrate; next, define the first conductive layer to form a gate; after that, form a dielectric layer on the gate; following that, form a channel over the gate; then, form a photo-resist block; form a second conductive layer; next, define the second conductive to form a source and a drain over the gate, and to form a photo-reflective layer on the photo-resist block; after that, form a protection layer thereon; following that, define the protection layer to form a first opening on the photo-reflective layer allowing part of the drain to be exposed, and to form a second opening on the photo-reflective layer allowing part of the photo-reflective layer to be exposed; last, form a transparent electrode being electrically connected to the drain and the photo-reflective layer via the first and the second opening respectively.

Transflective thin film transistor liquid crystal display panel and manufacturing method thereof

A liquid crystal display panel is provided. The LCD panel has a first substrate having at least a conductive material layer thereon, a second substrate having at least a repair line positioned in a predetermined area, and a liquid crystal layer positioned between the first substrate and the second substrate. The predetermined area is underneath the first substrate excluding the portions having the conductive material layer, thus reducing RC delay of the repair line.

Liquid crystal display panel having a repair line positioned only underneath the second portion of the non-display area

A liquid crystal display panel includes a first substrate, at least two first printed circuit boards, and at least one repair line. Each of the first printed circuit boards is utilized to output signals to a plurality of first conducting wires in parallel arranged on the first substrate. Additionally, the repair line has a first part located on the first substrate, a second part located on each of the first printed circuit boards, and a third part located on a connecting region between the first printed circuit boards.

Liquid crystal display panel including two PGB for outputting signals to the same conductive wires and a repair line

A method for fabricating source/drain and gate of a TFT (thin film transistor) array is disclosed herein. After depositing multi-layer structures according to the present invention, an etching process is performed to define source/drain or gate of a TFT array and an excellent taper profile is easily obtained even though only the prior art etchant is used. The method for depositing multi-layer structures includes the following steps. Firstly, form a major conductive metallic layer on the substrate or on the previous layers depending on whether gate or source/drain bus is to be formed, then form a barrier layer on the metallic layer with dopant doped into the barrier layer. It is noted that the concentration of the dopant has a gradient distribution, and has a maximum value at the edge of the barrier layer adjacent to the metallic layer. The first edge of the barrier layer adjacent to the metallic layer has a first dopant concentration, and the second edge of the barrier layer farther from the metallic layer has a second dopant concentration. The first dopant concentration is greater than the second dopant concentration. A special feature of this structure is that the wet etching rate of the doped barrier layer can be modulated by the doping concentration. Specifically, the higher the doping concentration, the lower the etching rate is preferred. Because the etching rate of the barrier layer is gradient changed by modulating the doping concentration during film deposition, the taper profile of the barrier layer will be automatically formed without the adjustment of the adhesion to the resist mask. It makes the etching chemistry less complicated and the profile is not sensitive to the bath life. Another feature of this method is that the etching rate of the barrier layer should be higher than the major metallic conductive layer to avoid the negative slope of the profile.

Method for forming TFT array bus

Apparatus for testing flat panel display (liquid crystal display) panel is disclosed herein. Testing apparatus for sending a plurality of electrical signals to a plurality of pads of a display panel, the testing apparatus includes the following devices. A plurality of probe pins is used to contact the plurality of pads of the display panel. The amount of the plurality of probe pins in the present invention is larger than the amount of the plurality of pads, besides, the pitches between the plurality of probe pins is smaller than the width of etch of the plurality of pads of the display panel. The signal generating means is used to generate the signals to be sent to the plurality of pads of the display panel through the plurality of probe pins. The switching means is used to provide the conductive paths between the signal generating means and the plurality of probe pins.

Apparatus for testing flat panel display

The present invention includes forming a gate on a transparent substrate. A gate isolation layer is then formed on the gate. An amorphous silicon (a-Si) layer and n&plus; doped silicon layer are successively formed on the gate isolation layer. Then, the a-Si layer and the n&plus; doped silicon layer are patterned. A first, a second and a third metal layers are successively formed on the n&plus; doped silicon layer, thereby forming a multi-metal layer structure. Subsequently, a wet and a dry etching is utilized to etch the multi-metal layer, thereby defining the S/D electrodes. A passivation layer is deposited on the S/D structure.

Thin film transistor with a multi-metal structure and a method of manufacturing the same

The present invention includes forming a gate on a transparent substrate. A gate isolation layer is then formed on the gate. An amorphous silicon (a-Si) layer and n+ doped silicon layer are successively formed on the gate isolation layer. Then, the a-Si layer and the n+ doped silicon layer are patterned. A first, a second and a third metal layers are successively formed on the n+ doped silicon layer, thereby forming a multi-metal layer structure. Subsequently, a wet and a dry etching is utilized to etch the multi-metal layer, thereby defining the S/D electrodes. A passivation layer is deposited on the S/D structure.

Growing community of inventors

Tainan, Taiwan

Wen-Jyh Sah