Taiwan Semiconductor Manufacturing Comp. Ltd.

Wen-Jye Yue

Tzong-Sheng Chang

Pin-Shyne Chin

Hsien-Chin Peng

Bor-Zen Tien

Hsun-Chih Tsao

Chen-Cheng Chou

The invention forms a 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region). The method of the invention forms a 1T Static Random Access Memory (SRAM) that uses a resist mask to block a high concentration implant into the cell node region, but allows the high concentration implant into the bit line region to form a second (high concentration) bit line. The invention's 1T SRAM, with the low concentration cell node, has reduced p-n junction leakage at the cell node and increase date retention time.

Low leakage one transistor static random access memory

This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N&plus; source and drain regions and the N&plus; polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an underlying titanium layer during rapid thermal anneal. The process begins by providing a substrate structure having a gate thereon. A titanium layer is deposited over the substrate structure and the gate. Mixing ions are implanted through the titanium layer into source and drain regions adjacent to the gate. A titanium nitride barrier layer is deposited on the titanium layer. The substrate structure is rapid thermal annealed causing the titanium layer to react with the underlying silicon to form silicide. The substrate structure is selectively etched to remove the titanium nitride barrier layer and unreacted titanium. A second rapid thermal anneal is performed.

Method for salicide process using a titanium nitride barrier layer

A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.

Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits

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Hsinchu, Taiwan

Wen-Jye Yue