Via Technologies, Inc.

Wen-Juin Huang

Chung-Ching Huang

Cheng-Wei Huang

Jui-Ming Wei

Chia-Ming Hsu

Chien-Ping Chung

Hao-Lin Lin

Chin-Han Chang

Chung-Chin Huang

Liang-Cheng Mai

The invention provides a method for power management for a computer system. In one embodiment, the computer system comprises a system controller, a chipset, and a battery coupled to the chipset via a system management bus. First, a timer of the chipset is used to calculate an accumulated time value. When the accumulated time value exceeds a threshold value, the chipset is directed to send a system control interrupt to the system controller. After the system controller receives the system control interrupt, the system controller is triggered to detect a power level supplied by the battery via the system management bus.

Method for power management for computer system

A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Method for accessing memory data

For saving power of a central processing unit at a Cpower level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the Cpower level. Afterwards, in response to a bus master request, the central processing unit is switched from the Cpower level to a transitional Cpower level while keeping the arbitrator disabled, and then switched from the transitional Cpower level to a Cpower level while enabling the arbitrator to process the bus master request.

Method and system for saving power of central processing unit

A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.

Method for power management of central processing unit and system thereof

A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Power saving method of central processing unit

Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.

Growing community of inventors

Taipei County, Taiwan

Wen-Juin Huang