Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Wen-Juh Kang

Yu-Chu Chen

Chen-Yang Pan

Yen-Chung Chen

Yi-Lin Lee

Yen-Chung Tony Chen

Hsin-Han Han

Cheng-Hung Wu

Liang-Hung Chen

Jung-Chi Huang

Hsun-Wei Kao

Man-Pio Lam

Ting-Hao Wang

Ming-Hsien Tsai

Jeng-Hung Tsai

Hua-Shih Liao

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

Analog to digital converter device and method for controlling calibration circuit

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

Analog to digital converter device and method for calibrating clock skew

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.

Communication receiving device and clock data recovery method

An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.

Analog-to-digital converter device and method for calibrating clock skew

An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries.

Analog to digital converter device and method of calibrating clock skew

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.

Eye diagram measurement device and eye diagram measurement method

A signal transmission device includes a transceiver circuitry and a control circuitry. The transceiver circuitry is configured to receive first device data from an external device through a channel. The control circuitry is configured to calculate a least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device.

Signal transmission device and linking method thereof

A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

Device and method for recovering clock and data

A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

Sampling phase adjustment device and adjusting method thereof

A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Clock and data recovery module

A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.

Receiving device and signal conversion method

An adjustable signal equalization device includes an equalizer circuitry, an analog-to-digital converter (ADC), a calculation circuitry, and a comparator circuitry. The equalizer circuitry has a transfer function, and processes an input signal based on the transfer function to generate an output signal. The ADC generates a digital signal according to the output signal. The calculation circuitry performs an accumulation according to the first digital signal to generate a first accumulated value and a second accumulated value, and generates a first detection signal and a second detection signal according to the first accumulated value and the second accumulated value. The comparator circuitry compares the first detection signal with the second detection signal to output a control signal to the equalizer circuit if the first detection signal is different from the second detection signal, in order to adjust the transfer function.

Adjustable signal equalization device and adjustment method thereof

An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.

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Hsinchu, Taiwan

Wen-Juh Kang